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HT66F016 датащи(PDF) 37 Page - Holtek Semiconductor Inc |
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HT66F016 датащи(HTML) 37 Page - Holtek Semiconductor Inc |
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37 / 116 page ![]() HT66F016/HT66F017/HT68F016/HT68F017 Rev. 1.00 37 May 14, 2012 N O R M A L M o d e S L E E P 0 M o d e S L E E P 1 M o d e I D L E 0 M o d e I D L E 1 M o d e S L O W M o d e C K S 2 ~ C K S 0 ¹ 0 0 0 B , 0 0 1 B a s H L C L K = 0 o r H L C L K = 1 W D T a n d L V D a r e a l l o f f I D L E N = 0 H A L T i n s t r u c t i o n i s e x e c u t e d W D T o r L V D i s o n I D L E N = 0 H A L T i n s t r u c t i o n i s e x e c u t e d I D L E N = 1 , F S Y S O N = 0 H A L T i n s t r u c t i o n i s e x e c u t e d I D L E N = 1 , F S Y S O N = 1 H A L T i n s t r u c t i o n i s e x e c u t e d SLOW Mode to NORMAL Mode Switching In SLOW Mode the system uses the LIRC low speed system oscillator. To switch back to the NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set to ²1² or HLCLK bit is ²0², but CKS2~CKS0 is set to ²010², ²011², ²100², ²101², ²110² or ²111². As a certain amount of time will be required for the high frequency clock to stabilise, the status of the HTO bit is checked. The amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. Entering the SLEEP0 Mode There is only one way for the device to enter the SLEEP0 Mode and that is to execute the ²HALT² instruc- tion in the application program with the IDLEN bit in SMOD register equal to ²0² and the WDT and LVD both off. When this instruction is executed under the condi- tions described above, the following will occur: · The system clock, WDT clock and Time Base clock will be stopped and the application program will stop at the ²HALT² instruction. · The Data Memory contents and registers will maintain their present condition. · The WDT will be cleared and stopped no matter if the WDT clock source originates from the fSUB clock or from the system clock. · The I/O ports will maintain their present conditions. · In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. |
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