DM9302 datasheet(33/64 Pages) DAVICOM

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DM9302

10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus

Preliminary datasheet

DM9302-15-DS-P01

July 30, 2009

6.51 Memory Data Write Command with Address Increment Register (F8H)

When register FFH bit 7 is “0”, register FBH value will be returned to 0000H, if 16K-byte boundary is reached.

Bit

Name

Default

Description

7:0

MWCMD

X,WO

Write Data to TX SRAM

After the write of this command, the write pointer is increased by 1, 2, or 4, depends

on the operator mode. (8-bit, 16-bit,32-bit respectively)

6.52 Memory Data Write Address Register (FAH)

When register FFH bit 7 is “0”, register FBH and FAH can be used as memory byte address to write internal 64K-byte

memory.

When register FFH bit 7 is “1”, register FBH and FAH are reserved. The processor port transmit memory address is generated

by DM9302 automatically.

Bit

Name

Default

Description

7:0

MDWAL

PHS0,RW Memory Data Write_ address Low Byte[7:0]

6.53 Memory Data Write Address Register (FBH)

Bit

Name

Default

Description

7:0

MDWAH

PHS0,RW Memory Data Write Byte Address High Byte[15:8]

6.54 TX Packet Length Registers (FCH~FDH)

Bit

Name

Default

Description

7:0

TXPLH

PHS0,RW TX Packet Length High byte

7:0

TXPLL

PHS0,RW TX Packet Length Low byte

6.55 Interrupt Status Register (FEH)

Bit

Name

Default

Description

IOMODE

T0, RO

Width Processor Data Bus

0: 16-bit mode

1: 8-bit mode

RESERVED

PHS0,RO

Reserved

LNKCHG

PHS0,RW/C1

Link Status Change of port 0 or 1

CNT_ERR

PHS0,RW/C1

Memory Management error

ROO

PHS0,RW/C1

Receive Overflow Counter Overflow

ROS

PHS0,RW/C1

Receive Overflow

PHS0,RW/C1

Packet Transmitted

PHS0,RW/C1

Packet Received

6.56 Interrupt Mask Register (FFH)

Bit

Name

Default

Description

TXRX_EN

PHS0,RW

Enable the SRAM read/write pointer used as transmit /receive address.

RESERVED

P0,RO

Reserved

LNKCHGI

PHS0,RW

Enable Link Status Change of port 0 or 1Interrupt

CNT_ERR

PHS0,RW/C1

Enable Memory Management error interrupt

ROOI

PHS0,RW

Enable Receive Overflow Counter Overflow Interrupt

ROI

PHS0,RW

Enable Receive Overflow Interrupt

PTI

PHS0,RW

Enable Packet Transmitted Interrupt

PRI

PHS0,RW

Enable Packet Received Interrupt

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