DM9302

10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus

Preliminary datasheet

3

DM9302-15-DS-P01

July 30, 2009

6.5 RX Status Register (06H) .............................................................................................................................. 18

6.6 Receive Overflow Counter Register (07H) .................................................................................................. 18

6.7 Flow Control Register (0AH)......................................................................................................................... 18

6.8 EEPROM & PHY Control Register (0BH) ..................................................................................................... 18

6.9 EEPROM & PHY Address Register (0CH) ................................................................................................... 19

6.10 EEPROM & PHY Data Registers (0DH~0EH)............................................................................................. 19

6.11 Link Change Control Register (0FH) ......................................................................................................... 19

6.12 Processor Port Physical Address Registers (10H~15H) ......................................................................... 19

6.13 Processor Port Multicast Address Registers (16H~1DH)........................................................................ 19

6.14 RX Packet Length Low Register ( 20H ) .................................................................................................... 20

6.15 RX Packet Length High Register ( 21H ) ................................................................................................... 20

6.16 RX Additional Status Register ( 26H ) ....................................................................................................... 20

6.17 RX Additional Control Register ( 27H )...................................................................................................... 20

6.18 Vendor ID Registers (28H~29H) ................................................................................................................. 20

6.19 Chip Revision Register (2CH) .................................................................................................................... 20

6.20 Transmit Check Sum Control Register (31H) ........................................................................................... 20

6.21 Receive Check Sum Control Status Register (32H)................................................................................. 21

6.22 uP Data Bus driving capability Register (38H) ......................................................................................... 21

6.23 IRQ Pin Control Register (39H) .................................................................................................................. 21

6.24 TX/RX Memory Size Control Register (3FH) ............................................................................................. 22