DM9302 datasheet(18/64 Pages) DAVICOM

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DM9302

10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus

Preliminary datasheet

DM9302-15-DS-P01

July 30, 2009

6.3 TX Control Register (02H)

Bit

Name

Default

Description

7:4

RESERVED

0,RO

Reserved

CRC_DIS2

PHS0,RW CRC Appends Disable for Packet Index 2

RESERVED

0,RO

Reserved

CRC_DIS1

PHS0,RW CRC Appends Disable for Packet Index 1

TXREQ

PHS0,RW TX Request. Auto clears after transmit completely

6.4 RX Control Register (05H)

Bit

Name

Default

Description

HASHALL

PHS0,RW

Filter All address in Hash Table

RESERVED PHS0,RW

Reserved

5:4

RESERVED PHS0,RW

Reserved

ALL

PHS0,RW

Pass All Multicast Packets

All received packets with bit 0 is “1” of Destination Address (DA) field are accepted

and save to receive memory.

RESERVED PHS0,RW

Reserved

PRMSC

PHS0,RW

Promiscuous Mode

All received packets are accepted and save to receive memory without DA field filter.

RXEN

PHS0,RW

RX Enable

6.5 RX Status Register (06H)

Bit

Name

Default

Description

7:4

RESERVED

0,RO

Reserved

3:2

SRCP

0,RO

Source Port Number

PH0,RO

CRC Error

It is set to indicate that the received frame ends with a CRC error

RESERVED

0,RO

Reserved

6.6 Receive Overflow Counter Register (07H)

Bit

Name

Default

Description

RXFU

PHS0,R/C

Receive Overflow Counter Overflow

This bit is set when the ROC has an overflow condition

6:0

ROC

PHS0,R/C

Receive Overflow Counter

This is a statistic counter to indicate the received packet count upon FIFO overflow

6.7 Flow Control Register (0AH)

Bit

Name

Default

Description

7:6

RESERVED

0,RO

Reserved

FLOW_EN

PHS0,RW

RX Flow Control Enable

Enables the pause packet for high/low water threshold control

4:0

RESERVED

0,RO

Reserved

6.8 EEPROM & PHY Control Register (0BH)

Bit

Name

Default

Description

7:6

RESERVED

0,RO

Reserved

REEP

PH0,RW

Reload EEPROM. Driver needs to clear it up after the operation completes

WEP

PH0,RW

Write EEPROM Enable

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