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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DM9302 датащи(PDF) 37 Page - Davicom Semiconductor, Inc. |
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DM9302 датащи(HTML) 37 Page - Davicom Semiconductor, Inc. |
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37 / 64 page  DM9302 10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus Preliminary datasheet 37 DM9302-15-DS-P01 July 30, 2009 8. PHY REGISTERS MII Register Description AD D Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset Loop back Speed select Auto-N Enable Power Down Isolate Restart Auto-N Full Duplex Coll. Test Reserved 00H CONTR OL 0 0 1 1 0 0 0 1 0 000_0000 T4 Cap. TX FDX Cap. TX HDX Cap. 10 FDX Cap. 10 HDX Cap. Reserved Pream. Supr. Auto-N Compl. Remote Fault Auto-N Cap. Link Status Jabber Detect Extd Cap. 01H STATU S 0 1 1 1 1 0000 1 0 0 1 0 0 1 02H PHYID1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 OUI_LSB VNDR_MDL MDL_REV 03H PHYID2 101110 001011 0000 04H Auto-Ne g. Advertis e Next Page FLP Rcv Ack Remote Fault Reserved FC Adv T4 Adv TX FDX Adv TX HDX Adv 10 FDX Adv 10 HDX Adv Advertised Protocol Selector Field 05H Link Part. Ability LP Next Page LP Ack LP RF Reserved LP FC LP T4 LP TX FDX LP TX HDX LP 10 FDX LP 10 HDX Link Partner Protocol Selector Field 06H Auto-Ne g. Expansi on Reserved Pardet Fault LP Next Pg Able Next Pg Able New Pg Rcv LP AutoN Cap. 10H Specifi ed Config. BP 4B5B BP SCR BP ALIGN BP_AD POK Reserv edr TX Reserv ed RMII mode Force 100LNK Rsvd. COL LED RPDCT R-EN Reset St. Mch Pream. Supr. Sleep mode Remote LoopOut 11H Specifi ed Conf/Sta t 100 FDX 100 HDX 10 FDX 10 HDX Reserv ed Revers ed Revers ed PHY ADDR [4:0] Auto-N. Monitor Bit [3:0] 12H 10T Conf/Sta t Rsvd LP Enable HBE Enable SQUE Enable JAB Enable Serial Reserved Polarity Reverse 13H PWDO R Reserved PD10D RV PD100l PDchip PDcrm PDaeq PDdrv PDecli PDeclo PD10 14H Specifie d config TSTSE 1 TSTSE 2 FORCE _TXSD FORCE _FEF PREA MBLEX TX10M _PWR NWAY _PWR Reserv ed MDIX_ CNTL AutoNe g_dlpbk Mdix_fix Value Mdix_d own MonSel 1 MonSel 0 Reserv ed PD_val ue 16H RCVER Receiver Error Counter 17H DIS_con nect Reversed Disconnect_counter 1DH PSCR Reversed PREA MBLE X AMPLIT UDE TX_P WR Reversed Key to Default In the register description that follows, the default column takes the form: <Reset Value>, <Access Type> / <Attribute(s)> Where: <Reset Value>: 1 Bit set to logic one 0 Bit set to logic zero X No default value <Access Type>: RO = Read only, RW = Read/Write <Attribute (s)>: SC = Self clearing, P = Value permanently set |
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