www.vishay.com

For technical questions within your region, please contact one of the following:

Document Number: 94542

6

Revision: 12-May-10

FC40SA50FKP

Vishay Semiconductors

Power MOSFET, 40 A

Fig. 12c - Unclamped Inductive Waveforms

Fig. 13a - Gate Charge Test Circuit

Fig. 13b - Basic Gate Charge Waveform

Fig. 13c - Peak Diode Recovery dV/dt Test Circuit

V

(BR)DSS

I

AS

t

p

-

+

D.U .T.

V

GS

1 mA

I

D

R

L

V

DS

V

G

Charge

V

GS

V

Q

G

Q

GD

Q

GS

+

-

+

+

+

-

-

-

• dV/dt controlled by R

G

• Driver same type as D.U.T.

• I

• D.U.T. - Device under test

D.U.T.

Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

1

2

4

3

R

G

V

DD