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PCF2123TS датащи(PDF) 21 Page - NXP Semiconductors

номер детали PCF2123TS
подробное описание детали  SPI Real time clock/calendar Time keeping application
PDF  63 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
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PCF2123TS датащи(HTML) 21 Page - NXP Semiconductors

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PCF2123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 27 April 2011
21 of 63
NXP Semiconductors
PCF2123
SPI Real time clock/calendar
The minute and second flag (bit MSF) is set logic 1 when either the seconds or the
minutes counter increments according to the currently enabled interrupt. The flag can be
read and cleared by the interface. The status of bit MSF does not affect the INT pulse
generation. If the MSF flag is not cleared prior to the next coming interrupt period, an INT
pulse will still be generated.
The purpose of the flag is to allow the controlling system to interrogate the PCF2123 and
identify the source of the interrupt, i.e., minute or second, countdown timer or alarm.
The duration of both of these timers will be affected by the register Offset_register (see
Section 8.9). Only when the Offset_register has the value 00h the periods will be
consistent.
In this example, TI_TP is set to logic 1 resulting in 1
64 Hz wide interrupt pulse and the MSF flag is
not cleared after an interrupt.
Fig 14. INT example for MI and SI
Table 26.
Effect of bits MI and SI on INT generation
Minute interrupt (bit MI)
Second interrupt (bit SI)
Result
0
0
no interrupt generated
1
0
an interrupt once per minute
0
1
an interrupt once per second
1
1
an interrupt once per second
Table 27.
Effect of MI and SI on MSF
Minute interrupt (bit MI)
Second interrupt (bit SI)
Result
0
0
MSF never set
1
0
MSF set when minutes counter
increments
0
1
MSF set when seconds counter
increments
1
1
MSF set when seconds counter
increments
001aaf905
58
59
59
00
11
seconds counter
minutes counter
INT when SI enabled
MSF when SI enabled
INT when only MI enabled
MSF when only MI enabled
12
00
01



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