ST10F276Z5 datasheet(121/239 Pages) STMICROELECTRONICS

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ST10F276Z5

System reset

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19.6

Bidirectional reset

As shown in the previous sections, the RSTOUT pin is driven active (low level) at the

beginning of any reset sequence (synchronous/asynchronous hardware, software and

watchdog timer resets). RSTOUT pin stays active low beyond the end of the initialization

routine, until the protected EINIT instruction (End of Initialization) is completed.

The Bidirectional Reset function is useful when external devices require a reset signal but

cannot be connected to RSTOUT pin, because RSTOUT signal lasts during initialization. It

is, for instance, the case of external memory running initialization routine before the

execution of EINIT instruction.

Bidirectional reset function is enabled by setting bit 3 (BDRSTEN) in SYSCON register. It

only can be enabled during the initialization routine, before EINIT instruction is completed.

When enabled, the open drain of the RSTIN pin is activated, pulling down the reset signal,

for the duration of the internal reset sequence (synchronous/asynchronous hardware,

synchronous software and synchronous watchdog timer resets). At the end of the internal

reset sequence the pull down is released and:

●

After a Short Synchronous Bidirectional Hardware Reset, if RSTF is sampled low 8

TCL periods after the internal reset sequence completion (refer to Figure 28 and

Figure 29), the Short Reset becomes a Long Reset. On the contrary, if RSTF is

sampled high the device simply exits reset state.

●

After a Software or Watchdog Bidirectional Reset, the device exits from reset. If RSTF

remains still low for at least 4 TCL periods (minimum time to recognize a Short

Hardware reset) after the reset exiting (refer to Figure 34 and Figure 35), the Software

or Watchdog Reset become a Short Hardware Reset. On the contrary, if RSTF remains

low for less than 4 TCL, the device simply exits reset state.

The Bidirectional reset is not effective in case RPD is held low, when a Software or

Watchdog reset event occurs. On the contrary, if a Software or Watchdog Bidirectional reset

event is active and RPD becomes low, the RSTIN pin is immediately released, while the

internal reset sequence is completed regardless of RPD status change (1024 TCL).

Note:

The bidirectional reset function is disabled by any reset sequence (bit BDRSTEN of

SYSCON is cleared). To be activated again it must be enabled during the initialization

routine.

WDTCON flags

Similarly to what already highlighted in the previous section when discussing about Short

reset and the degeneration into Long reset, similar situations may occur when Bidirectional

reset is enabled. The presence of the internal filter on RSTIN pin introduces a delay: when

RSTIN is released, the internal signal after the filter (see RSTF in the drawings) is delayed,

so it remains still active (low) for a while. It means that depending on the internal clock

speed, a short reset may be recognized as a long reset: the WDTCON flags are set

accordingly.

Besides, when either Software or Watchdog bidirectional reset events occur, again when the

RSTIN pin is released (at the end of the internal reset sequence), the RSTF internal signal

(after the filter) remains low for a while, and depending on the clock frequency it is

recognized high or low: 8TCL after the completion of the internal sequence, the level of

RSTF signal is sampled, and if recognized still low a Hardware reset sequence starts, and

WDTCON will flag this last event, masking the previous one (Software or Watchdog reset).

Typically, a Short Hardware reset is recognized, unless the RSTIN pin (and consequently

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