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IXP45X датащи(PDF) 121 Page - Intel Corporation |
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IXP45X датащи(HTML) 121 Page - Intel Corporation |
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121 / 148 page ![]() Intel® IXP45X and Intel® IXP46X Product Line of Network Processors August 2006 Datasheet Document Number: 306261-004US 121 Datasheet—Intel® IXP45X and Intel® IXP46X Product Line of Network Processors Figure 24. Source Synchronous SMII Input Timings Table 59. Source Synchronous SMII Input Timings Values Symbol Parameter Min. Max. Units Notes T3 SMII_RXD and SMII_RXSYNC setup time prior to rising edge of SMII_RXCLK 1.5 ns 1 T4 SMII_RXD and SMII_RXSYNC hold time after the rising edge of SMII_CLK 1ns 1 Notes: 1. Timing was designed for a system load between 5pF and 15pF Figure 25. MII Output Timings Table 60. MII Output Timings Values Symbol Parameter Min. Max. Units Notes T1 Clock to output delay for ETH_TXDATA and ETH_TXEN. 12.5 ns 1, 2 T2 ETH_TXDATA and ETH_TXEN hold time after ETH_TXCLK. 1.5 ns 2 Notes: 1. These values satisfy t the MII specification requirement of 0 ns to 25 ns clock to output delay. 2. Timing was designed for a system load between 5 pF and 15 pF. SMII_RXCLK SMII_INPUTS T 3 T 4 A9580-01 eth_tx_clk eth_tx_data[7:0] eth_tx_en eth_crs T1 T2 |
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