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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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5000 датащи(PDF) 18 Page - Intel Corporation |
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5000 датащи(HTML) 18 Page - Intel Corporation |
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18 / 104 page  Electrical Specifications 18 Dual-Core Intel® Xeon® Processor 5000 Series Datasheet 2.4.2 Phase Lock Loop (PLL) and Filter VCCA and VCCIOPLL are power sources required by the PLL clock generators on the Dual- Core Intel Xeon Processor 5000 series. Since these PLLs are analog in nature, they require low noise power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core timings (that is, maximum frequency). To prevent this degradation, these supplies must be low pass filtered from VTT. The AC low-pass requirements are as follows: • < 0.2 dB gain in pass band • < 0.5 dB attenuation in pass band < 1 Hz • > 34 dB attenuation from 1 MHz to 66 MHz • > 28 dB attenuation from 66 MHz to core frequency The filter requirements are illustrated in Figure 2-1. For recommendations on implementing the filter, refer to the appropriate platform design guidelines. Notes: 1. Diagram not to scale. 2. No specifications for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05 MHz. 4. fcore represents the maximum core frequency supported by the platform. Figure 2-1. Phase Lock Loop (PLL) Filter Requirements CS00141 0 dB -28 dB -34 dB 0.2 dB forbidden zone -0.5 dB forbidden zone 1 MHz 66 MHz fcore fpeak 1 Hz DC passband high frequency band |
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