5000 datasheet(66/104 Pages) INTEL

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Signal Definitions

Dual-Core Intel® Xeon® Processor 5000 Series Datasheet

PWRGOOD

PWRGOOD (Power Good) is an input. The processor requires this signal to be a clean

indication that all processor clocks and power supplies are stable and within their

specifications. “Clean” implies that the signal will remain low (capable of sinking

leakage current), without glitches, from the time that the power supplies are turned

on until they come within specification. The signal must then transition monotonically

to a high state.PWRGOOD can be driven inactive at any time, but clocks and power

must again be stable before a subsequent rising edge of PWRGOOD. It must also

meet the minimum pulse width specification in Table 2-15, and be followed by a

1-10 ms RESET# pulse.

The PWRGOOD signal must be supplied to the processor; it is used to protect internal

circuits against voltage sequencing issues. It should be driven high throughout

boundary scan operation.

REQ[4:0]#

I/O

REQ[4:0]# (Request Command) must connect the appropriate pins of all processor

FSB agents. They are asserted by the current bus owner to define the currently

active transaction type. These signals are source synchronous to ADSTB[1:0]#.

Refer to the AP[1:0]# signal description for details on parity checking of these

signals.

RESET#

Asserting the RESET# signal resets all processors to known states and invalidates

their internal caches without writing back any of their contents. For a power-on

Reset, RESET# must stay active for at least 1 ms after VCC and BCLK have reached

their proper specifications. On observing active RESET#, all FSB agents will deassert

their outputs within two clocks. RESET# must not be kept asserted for more than 10

ms while PWRGOOD is asserted.

A number of bus signals are sampled at the active-to-inactive transition of RESET#

for power-on configuration. These configuration options are described in the

Section 7.1.

This signal does not have on-die termination and must be terminated on the

system board.

RS[2:0]#

RS[2:0]# (Response Status) are driven by the response agent (the agent responsible

for completion of the current transaction), and must connect the appropriate pins of

all processor FSB agents.

RSP#

RSP# (Response Parity) is driven by the response agent (the agent responsible for

completion of the current transaction) during assertion of RS[2:0]#, the signals for

which RSP# provides parity protection. It must connect to the appropriate pins of all

processor FSB agents.

A correct parity signal is high if an even number of covered signals are low and low if

an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also high,

since this indicates it is not being driven by any agent guaranteeing correct parity.

SKTOCC#

SKTOCC# (Socket occupied) will be pulled to ground by the processor to indicate that

the processor is present. There is no connection to the processor silicon for this

signal.

SMI#

SMI# (System Management Interrupt) is asserted asynchronously by system logic.

On accepting a System Management Interrupt, processors save the current state and

enter System Management Mode (SMM). An SMI Acknowledge transaction is issued,

and the processor begins program execution from the SMM handler.

If SMI# is asserted during the deassertion of RESET# the processor will tri-state its

outputs.

STPCLK#

STPCLK# (Stop Clock), when asserted, causes processors to enter a low power Stop-

Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops

providing internal clock signals to all processor core units except the FSB and APIC

units. The processor continues to snoop bus transactions and service interrupts while

in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal

clock to all units and resumes execution. The assertion of STPCLK# has no effect on

the bus clock; STPCLK# is an asynchronous input.

TCK

TCK (Test Clock) provides the clock input for the processor Test Bus (also known as

the Test Access Port).

TDI

TDI (Test Data In) transfers serial test data into the processor. TDI provides the

serial input needed for JTAG specification support.

TDO

TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the

serial output needed for JTAG specification support.

TEST_BUS

Other

Must be connected to all other processor TEST_BUS signals in the system. See the

appropriate platform design guideline for termination details.

Table 5-1.

Signal Definitions (Sheet 6 of 8)

Name

Type

Description

Notes

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