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Thermal Specifications

Dual-Core Intel® Xeon® Processor 5000 Series Datasheet

Figure 6-2; Table 6-3 and Table 6-6) is indicative of a constrained thermal environment

(that is, 1U form factor). Because of the reduced cooling capability represented by this

thermal solution, the probability of TCC activation and performance loss is increased.

Additionally, utilization of a thermal solution that does not meet Thermal Profile B will

violate the thermal specifications and may result in permanent damage to the

processor. Intel has developed these thermal profiles to allow OEMs to choose the

thermal solution and environmental parameters that best suit their platform

implementation. Refer to the Dual-Core Intel® Xeon® Processor 5000 Series Thermal/

Mechanical Design Guidelines for details on system thermal solution design, thermal

profiles and environmental considerations.

The Dual-Core Intel Xeon Processor 5063 (MV) supports a single Thermal Profile

targeted at volumetrically constrained thermal environments (for example, blades, 1U

form factors.) With this Thermal Profile, it’s expected that the Thermal Control Circuit

(TCC) would only be activated for very brief periods of time when running the most

power-intensive applications. Refer to the Dual-Core Intel® Xeon® Processor 5000

Series Thermal/Mechanical Design Guidelines for further details.

The upper point of the thermal profile consists of the Thermal Design Power (TDP)

defined in Table 6-1, Table 6-4, Table 6-7 and the associated TCASE value. It should be

noted that the upper point associated with Thermal Profile B (x = TDP and y =

TCASE_MAX_B @ TDP) represents a thermal solution design point. In actuality the

processor case temperature will not reach this value due to TCC activation (refer to

Figure 6-1 and Figure 6-2). The lower point of the thermal profile consists of x =

P_profile_min and y = TCASE_MAX @ P_profile_min. P_profile_min is defined as the

processor power at which TCASE , calculated from the thermal profile, is equal to 50

° C.

The case temperature is defined at the geometric top center of the processor IHS.

Analysis indicates that real applications are unlikely to cause the processor to consume

maximum power dissipation for sustained time periods. Intel recommends that

complete thermal solution designs target the Thermal Design Power (TDP) indicated in

Table 6-1, Table 6-4 and Table 6-7, instead of the maximum processor power

consumption. The Thermal Monitor feature is intended to help protect the processor in

the event that an application exceeds the TDP recommendation for a sustained time

period. For more details on this feature, refer to Section 6.2. To ensure maximum

flexibility for future requirements, systems should be designed to the Flexible

Motherboard (FMB) guidelines, even if a processor with lower power dissipation is

currently planned. The Thermal Monitor feature must be enabled for the

processor to remain within its specifications.

Notes:

These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure

the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at

specified ICC. Please refer to the loadline specifications in Chapter 2, “Electrical Specifications”.

Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the

maximum power that the processor can dissipate. TDP is measured at maximum TCASE.

These specifications are based on final silicon validation/characterization.

Power specifications are defined at all VIDs found in Table 2-10. The Dual-Core Intel Xeon Processor 5000

series may be shipped under multiple VIDs for each frequency.

FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor

frequency requirements.

Table 6-1.

Dual-Core Intel Xeon Processor 5000 Series (1066 MHz) Thermal

Specifications

Core Frequency

Thermal

Design Power

(W)

Minimum

TCASE

(°C)

Maximum TCASE

(°C)

Notes

Launch to FMB

130

Refer to Figure 6-1; Table 6-2; Table 6-3

1, 2, 3, 4, 5

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