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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LPC1102 датащи(PDF) 15 Page - NXP Semiconductors |
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LPC1102 датащи(HTML) 15 Page - NXP Semiconductors |
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15 / 38 page  LPC1102 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Objective data sheet Rev. 00 — 23 June 2010 15 of 38 NXP Semiconductors LPC1102 32-bit ARM Cortex-M0 microcontroller 7.15.5 AHBLite The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main static RAM, and the Boot ROM. 7.15.6 External interrupt inputs All GPIO pins can be level or edge sensitive interrupt inputs. 7.15.7 Memory mapping control The Cortex-M0 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register contained in the NVIC. The vector table may be located anywhere within the bottom 1 GB of Cortex-M0 address space. The vector table must be located on a 128 word (512 byte) boundary. 7.16 Emulation and debugging Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four breakpoints and two watchpoints is supported. Remark: Care must be taken when using the SPI because the SPI clock SCK and the serial wire debug clock SWCLK share the same pin on the WLCSP16 package. Once the SPI is enabled, the serial wire debugger is no longer available. |
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