LPC1102 datasheet(13/38 Pages) NXP

13 / 38 page

LPC1102

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Objective data sheet

Rev. 00 — 23 June 2010

13 of 38

NXP Semiconductors

LPC1102

32-bit ARM Cortex-M0 microcontroller

minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle.

The PLL is turned off and bypassed following a chip reset and may be enabled by

software. The program must configure and activate the PLL, wait for the PLL to lock, and

then connect to the PLL as a clock source. The PLL settling time is 100

μs.

7.14.3 Wake-up process

The LPC1102 begin operation at power-up by using the 12 MHz IRC oscillator as the

clock source. This allows chip operation to resume quickly. If an external clock or the PLL

is needed by the application, software will need to enable these features and wait for them

to stabilize before they are used as a clock source.

7.14.4 Power control

The LPC1102 support a variety of power control features. There are two special modes of

processor power reduction: Sleep mode and Deep-sleep mode. The CPU clock rate may

also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or

altering the CPU clock divider value. This allows a trade-off of power versus processing

speed based on application requirements. In addition, a register is provided for shutting

down the clocks to individual on-chip peripherals, allowing fine tuning of power

consumption by eliminating all dynamic power use in any peripherals that are not required

for the application. Selected peripherals have their own clock divider which provides even

better power control.

7.14.4.1

Sleep mode

When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep

mode does not need any special sequence but re-enabling the clock to the ARM core.

In Sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and may generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, and internal

buses.

7.14.4.2

Deep-sleep mode

In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut

down except for the watchdog oscillator and the BOD circuit, which can be configured to

remain running in Deep-sleep mode to allow a reset initiated by a timer or BOD event.

Deep-sleep mode allows for additional power savings.

The GPIO pins (6 pins total, see Table 3) serve as external wake-up pins to a dedicated

start logic to wake up the chip from Deep-sleep mode.

The clock source should be switched to IRC before entering Deep-sleep mode unless the

watchdog oscillator remains running in Deep-sleep mode. The IRC can be switched on

and off glitch-free and provides a clean clock signal after start-up.

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