LPC1102 datasheet(7/38 Pages) NXP

7 / 38 page

LPC1102

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Objective data sheet

Rev. 00 — 23 June 2010

7 of 38

NXP Semiconductors

LPC1102

32-bit ARM Cortex-M0 microcontroller

7.5 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The

tight coupling to the CPU allows for low interrupt latency and efficient processing of late

arriving interrupts.

7.5.1 Features

• Controls system exceptions and peripheral interrupts.

• In the LPC1102, the NVIC supports 19 vectored interrupts including up to 6 inputs to

the start logic from individual GPIO pins.

Fig 3.

LPC1102 memory map

0x5000 0000

0x5001 0000

0x5002 0000

0x5020 0000

AHB peripherals

127 - 16 reserved

GPIO PIO1

7-4

0x5003 0000

0x5004 0000

reserved

11-8

15-12

GPIO PIO0

3-0

APB peripherals

0x4000 4000

0x4000 8000

0x4000 C000

0x4001 0000

0x4001 8000

0x4002 0000

0x4002 8000

0x4003 8000

0x4003 C000

0x4004 0000

0x4004 4000

0x4004 8000

0x4004 C000

0x4005 8000

0x4005 C000

0x4008 0000

0x4002 4000

0x4001 C000

0x4001 4000

0x4000 0000

WDT

32-bit counter/timer 0

32-bit counter/timer 1

ADC

UART

PMU

reserved

13 - 10 reserved

reserved

21 - 19 reserved

31 - 23 reserved

reserved

0x0000 0000

0 GB

0.5 GB

4 GB

1 GB

0x1000 2000

0x1FFF 0000

0x1FFF 4000

0x2000 0000

0x4000 0000

0x4008 0000

0x5000 0000

0x5020 0000

0xFFFF FFFF

reserved

APB peripherals

AHB peripherals

8 kB SRAM

0x1000 0000

LPC1102

0x0000 8000

32 kB on-chip flash

16 kB boot ROM

0x0000 0000

0x0000 0200

active interrupt vectors

+ 512 byte

002aaf526

reserved

SPI

16-bit counter/timer 1

16-bit counter/timer 0

IOCONFIG

system control

reserved

flash controller

0xE000 0000

0xE010 0000

private peripheral bus

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