LPC1102 datasheet(14/38 Pages) NXP

14 / 38 page

LPC1102

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 00 — 23 June 2010

14 of 38

NXP Semiconductors

LPC1102

32-bit ARM Cortex-M0 microcontroller

7.15 System control

7.15.1 Reset

Reset has four sources on the LPC1102: the RESET pin, the Watchdog reset, power-on

reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt

trigger input pin. Assertion of chip reset by any source, once the operating voltage attains

a usable level, starts the IRC and initializes the flash controller.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

7.15.2 Brownout detection

The LPC1102 includes four levels for monitoring the voltage on the VDD pin. If this voltage

falls below one of the four selected levels, the BOD asserts an interrupt signal to the

NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC

in order to cause a CPU interrupt; if not, software can monitor the signal by reading a

dedicated status register. Four additional threshold levels can be selected to cause a

forced reset of the chip.

7.15.3 Code security (Code Read Protection - CRP)

This feature of the LPC1102 allows user to enable different levels of security in the system

so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) can be

restricted. When needed, CRP is invoked by programming a specific pattern into a

dedicated flash location. IAP commands are not affected by the CRP.

There are three levels of Code Read Protection:

1. CRP1 disables access to the chip via the SWD and allows partial flash update

(excluding flash sector 0). This mode is useful when CRP is required and flash field

updates are needed but all sectors can not be erased.

2. CRP2 disables access to the chip via the SWD and only allows full flash erase and

update.

3. Running an application with level CRP3 selected fully disables any access to the chip

via the SWD pins.

Remark: The LPC1102 does not provide an ISP entry pin to be monitored at reset. For all

three CRP levels, the user’s application code must provide a flash update mechanism

which reinvokes ISP by defining a user-selected PIO pin for ISP entry.

7.15.4 APB interface

The APB peripherals are located on one APB bus.

CAUTION

If Code Read Protection (CRP1/2/3) is selected, no future factory testing can be performed

on the device.

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