KM416RD8ACD-RK80 datasheet(20/64 Pages) SAMSUNG

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Page 17

KM416RD8AC(D)/KM418RD8AC(D)

Direct RDRAM™

Rev. 1.01 Oct. 1999

Figure 12 shows examples of the PRER-to-PRER (RR13,

RR14) and PRER-to-ACT (RR9, RR10) command spacings

from Table 10. The RR15 and RR16 cases (PRER-to-PRER

to same or adjacent banks) are not shown, but are similar to

RR14. In general, the commands in ROW packets may be

spaced an interval tPACKET apart unless they are directed to

the same or adjacent banks or unless they are a similar

command type (both PRER or both ACT) directed to the

same device.

Row and Column Cycle Description

Activate: A row cycle begins with the activate (ACT) opera-

tion. The activation process is destructive; the act of sensing

the value of a bit in a bank’s storage cell transfers the bit to

the sense amp, but leaves the original bit in the storage cell

with an incorrect value.

Restore: Because the activation process is destructive, a

hidden operation called restore is automatically performed.

The restore operation rewrites the bits in the sense amp back

into the storage cells of the activated row of the bank.

Read/Write: While the restore operation takes place, the

sense amp may be read (RD) and written (WR) using

column operations. If new data is written into the sense amp,

it is automatically forwarded to the storage cells of the bank

so the data in the activated row and the data in the sense amp

remain identical.

Precharge: When both the restore operation and the column

operations are completed, the sense amp and bank are

precharged (PRE). This leaves them in the proper state to

begin another activate operation.

Intervals: The activate operation requires the interval

tRCD,MIN to complete. The hidden restore operation requires

the interval tRAS,MIN - tRCD,MIN to complete. Column read

and write operations are also performed during the tRAS,MIN

- tRCD,MIN interval (if more than about four column opera-

tions are performed, this interval must be increased). The

precharge operation requires the interval tRP,MIN to

complete.

Adjacent Banks: An RDRAM with an “s” designation

(256Kx32sx16/18) indicates it contains “split banks”. This

means the sense amps are shared between two adjacent

banks. The only exception is that sense amp 0, 15, 30, and

31are not shared. When a row in a bank is activated, the two

adjacent sense amps are connected to (associated with) that

bank and are not available for use by the two adjacent banks.

These two adjacent banks must remain precharged while the

selected bank goes through its activate, restore, read/write,

and precharge operations.

For example (referring to the block diagram of Figure 2), if

bank 5 is accessed, sense amp 4/5 and sense amp 5/6 will

both be loaded with one of the 512 rows (with 512 bytes

loaded into each sense amp from the 1Kbyte row - 256 bytes

to the DQA side and 256 bytes to the DQB side). While this

row from bank 5 is being accessed, no rows may be accessed

in banks 4 or 6 because of the sense amp sharing.

Figure 12: Row Packet Examples

CTM/CFM

DQA8..0

DQB8..0

COL4

..COL0

ROW2

..ROW0

T12

T13

T10

T14

T11

T15 T16

T20

T24

T28

T17

T21

T25

T29

T18

T22

T26

T30

T19

T23

T27

T31 T32

T36

T40

T44

T33

T37

T41

T45

T34

T38

T42

T46

T35

T39

T43

T47

PRER a0

ACT b0

tPACKET

PRER c0

a0 = {Da,Ba,Ra}

b0 = {Db,Bb,Rb}

c0 = {Da,Bc,Rc}

Different Device

Any Bank

Same Device

Non-adjacent Bank

RR13

RR14

PRER a0

PRER b0

ACT c0

b0 = {Db,Bb,Rb}

c0 = {Da,Bc,Rc}

Different Device

Any Bank

Same Device

Non-adjacent Bank

RR9

RR10

PRER a0

c0 = {Da,Ba+1Rc}

Same Device

Same Bank

RR16

c0 = {Da,Ba,Rc}

Same Device

Adjacent Bank

RR15

tPP

tPACKET

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