HT82K75REW datasheet(49/103 Pages) HOLTEK

49 / 103 page

HT82M75REW/HT82K75REW

Rev. 1.00

June 11, 2010

TXMAC

When the TXFIFO is triggered, the TXMAC gets the

data from TXFIFO to generate a 16-bit FCS and sends

the packet to the PHY layer of the TX immediately. If

necessary, TXMAC handles the retransmission, when

the acknowledgement packet is not received. The block

diagram of a TXMAC is shown below.

RXMAC

The RX PHY of the RF Transceiver filters signals and

tracks the synchronization symbols. If a packet passes

the filtering, RXMAC performs frame type parsing, ad-

dress recognition and FCS checking. If the destination

address is broadcast address or matches its own iden-

tity, configured by SREG0x05 to SREG0x08, and the

FCS check is passed, an interrupt is issued at

SREG0x31 [3] to indicate a valid packet is received.

Meanwhile, the frame length field of PHY header and

PHY payload will be stored in RXFIFO. Unqualified

packets are skipped.

RXFIFO0 and RXFIFO1 are mapped into the 64-byte

memory space from 0x300H to 0x33FH as Ping-Pong

FIFOs. If Ping-Pong RX mode is enabled by SREG0x34

[0], RXMAC automatically switches between RXFIFO0

and RXFIFO1 to store incoming frame whenever a new

packet comes. When the MCU host reads the long ad-

dress memory 0x300H, the RXMAC will change the flag

of SREG0x34 [1] automatically. For manually controlled

RX operation, if the value of the flag SREG0x34 [1] is

²0², the RXFIFO0 shall be read. Otherwise, the

RXFIFO1 shall be read.

In the above diagram, the current status of each frame is

represented in SREG0x30. SREG0x30 [7] means

²RXFIFO full² indicating the two RXFIFOs are occupied.

If the MCU host cannot read the RXFIFO in time, the

value of SREG0x30 [7] will be set to

²1². Once the MCU

host read the RXFIFO, the value of the SREG0x30 [7]

will be set to

²0² automatically.

The contents of the RXFIFO can be flushed only by the

following three ways: (1) the MCU host reads length

field of RXFIFO and the last byte of the packet, (2) the

host issues an RX flush, and (3) the software reset by

SREG0x2A [0]. Note that RXFIFO is ready to receive

next packet and all the data in RFIFO will be overwritten

after RXFIFO flushed.

TXMAC Block Diagram

RXMAC Block Diagram

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