MPC5200B_10 datasheet(66/72 Pages) FREESCALE

66 / 72 page

MPC5200B Data Sheet, Rev. 4

Freescale Semiconductor

3.3.2

Pull-up Requirements for the PCI Control Lines

If the PCI interface is NOT used (and internally disabled) the PCI control pins must be terminated as indicated by the PCI Local

Bus specification. This is also required for MOST/Graphics and Large Flash Mode.

PCI control signals always require pull-up resistors on the motherboard (not the expansion board) to ensure that they contain

stable values when no agent is actively driving the bus. This includes PCI_FRAME, PCI_TRDY, PCI_IRDY, PCI_DEVSEL,

PCI_STOP, PCI_SERR, PCI_PERR, and PCI_REQ.

3.3.3

Pull-up/Pull-down Requirements for MEM_MDQS Pins (SDRAM)

The MEM_MDQS[3:0] signals are not used with SDR memories and require pull-up or pull-down resistors in SDRAM mode.

3.3.4

Pull-up/Pull-down Requirements for MEM_MDQS Pins (DDR 16-bit

Mode)

The MEM_MDQS[1:0] signals are not used in DDR 16-bit mode and require pull-down resistors.

3.4

JTAG

The MPC5200B provides the user an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also provides a Common

On-Chip Processor (COP) Interface, which shares the IEEE 1149.1 JTAG port. The COP Interface provides access to the

MPC5200B's embedded Freescale (formerly Motorola) MPC603e e300 processor. This interface provides a means for

executing test routines and for performing software development and debug functions.

3.4.1

JTAG_TRST

Boundary scan testing is enabled through the JTAG interface signals. The JTAG_TRST signal is optional in the IEEE 1149.1

specification but is provided on all processors that implement the PowerPC architecture. To obtain a reliable power-on reset

performance, the JTAG_TRST signal must be asserted during power-on reset.

3.4.1.1

JTAG_TRST and PORRESET

The JTAG interface can control the direction of the MPC5200B I/O pads via the boundary scan chain. The JTAG module must

be reset before the MPC5200B comes out of power-on reset; do this by asserting JTAG_TRST before PORRESET is released.

For more details refer to the Reset and JTAG Timing Specification.

Figure 53. PORRESET vs. JTAG_TRST

3.4.1.2

Connecting JTAG_TRST

The wiring of the JTAG_TRST depends on the existence of a board-related debug interface. (see below)

JTAG_TRST

PORRESET

Required assertion of JTAG_TRST

Optional assertion of JTAG_TRST

MPC5200B датащи(PDF) 66 Page - Freescale Semiconductor, Inc