MPC5200B_10 datasheet(23/72 Pages) FREESCALE

23 / 72 page

MPC5200B Data Sheet, Rev. 4

Freescale Semiconductor

2. Minimum times are measured at the package pin with the load circuit, and maximum times are measured with the load circuit

as shown in the PCI Local Bus Specification.

3. REQ# and GNT# are point-to-point signals and have different input setup times than do bused signals. GNT# and REQ# have

a setup of 5 ns at 66 MHz. All other signals are bused.

4. See the timing measurement conditions in the PCI Local Bus Specification.

For Measurement and Test Conditions, see the PCI Local Bus Specification.

1.3.8

Local Plus Bus

The Local Plus Bus is the external bus interface of the MPC5200B. A maximum of eight configurable chip selects (CS) are

provided. There are two main modes of operation: non-MUXed (Legacy and Burst) and MUXED. The reference clock is the

PCI CLK. The maximum bus frequency is 66 MHz.

Definition of Acronyms and Terms:

•

WS = Wait State

•

DC = Dead Cycle

•

LB = Long Burst

•

DS = Data Size in Bytes

•tPCIck = PCI clock period

•tIPBIck = IPBI clock period

Figure 10. Timing Diagram—IPBI and PCI clock (example ratio: 4:1)

1.3.8.1

Non-MUXed Mode

Table 24. Non-MUXed Mode Timing

Sym

Description

Min

Max

Units

Notes

SpecID

tCSA

PCI CLK to CS assertion

4.6

10.6

—A7.1

tCSN

PCI CLK to CS negation

2.9

7.0

—A7.2

CS pulse width

(2 + WS) × tPCIck

(2 +WS) ×tPCIck

(1)

A7.3

ADDR valid before CS assertion

tIPBIck

tPCIck

—A7.4

ADDR hold after CS negation

tIPBIck

—ns

(2)

A7.5

OE assertion before CS assertion

—4.8

—A7.6

OE negation before CS negation

—2.7

—A7.7

RW valid before CS assertion

tPCIck

—ns

—A7.8

RW hold after CS negation

tIPBIck

—ns

—A7.9

DATA output valid before CS assertion

tIPBIck

—ns

—

A7.10

DATA output hold after CS negation

tIPBIck

—ns

—

A7.11

PCI CLK

IPBI CLK

tIPBIck

tPCIck

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