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MPC5200B датащи(PDF) 40 Page - Freescale Semiconductor, Inc

номер детали MPC5200B
подробное описание детали  SDRAM/DDR Memory Controller
PDF  72 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC5200B датащи(HTML) 40 Page - Freescale Semiconductor, Inc

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MPC5200B Data Sheet, Rev. 4
40
Freescale Semiconductor
Figure 30. Ethernet Timing Diagram—MII Serial Management
1.3.11
USB
NOTE
Output timing is specified at a nominal 50 pF load.
Table 34. MII Serial Management Channel Signal Timing
Sym
Description
Min
Max
Unit
SpecID
t10
MDC falling edge to MDIO output delay
0
25
ns
A9.10
t11
MDIO (input) to MDC rising edge setup
10
—
ns
A9.11
t12
MDIO (input) to MDC rising edge hold
10
—
ns
A9.12
t13
MDC pulse width high(1)
1 MDC is generated by MPC5200B with a duty cycle of 50% except when MII_SPEED in the FEC MII_SPEED control
register is changed during operation. See the MPC5200B User’s Manual (MPC5200BUM).
160
—
ns
A9.13
t14
MDC pulse width low(1)
160
—
ns
A9.14
t15
MDC period(2)
2 The MDC period must be set to a value of less than or equal to 2.5 MHz (to be compliant with the IEEE MII
characteristic) by programming the FEC MII_SPEED control register. See the MPC5200B User’s Manual
(MPC5200BUM).
400
—
ns
A9.15
Table 35. Timing Specifications—USB Output Line
Sym
Description
Min
Max
Units
SpecID
1
USB Bit width(1)
1 Defined in the USB config register, (12 Mbit/s or 1.5 Mbit/s mode).
83.3
667
ns
A10.1
2
Transceiver enable time
83.3
667
ns
A10.2
3
Signal falling time
—
7.9
ns
A10.3
4
Signal rising time
—
7.9
ns
A10.4
t14
t13
t12
MDC (Output)
MDIO (Input)
MDIO (Output)
t11
t10
t15



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