MPC5200B_10 datasheet(29/72 Pages) FREESCALE

29 / 72 page

MPC5200B Data Sheet, Rev. 4

Freescale Semiconductor

All ATA transfers are programmed in terms of system clock cycles (IP bus clocks) in the ATA Host Controller timing registers.

This puts constraints on the ATA protocols and their respective timing modes in which the ATA Controller can communicate

with the drive.

Faster ATA modes (i.e., UDMA 0, 1, 2 ) are supported when the system is running at a sufficient frequency to provide adequate

data transfer rates. Adequate data transfer rates are a function of the following:

•

The MPC5200B operating frequency (IP bus clock frequency)

•

Internal MPC5200B bus latencies

•

Other system load dependent variables

The ATA clock is the same frequency as the IP bus clock in MPC5200B. See the MPC5200B User’s Manual (MPC5200B).

NOTE

All output timing numbers are specified for nominal 50 pF loads.

Table 27. PIO Mode Timing Specifications

Sym

PIO Timing Parameter

Min/Max

(ns)

Mode 0

(ns)

Mode 1

(ns)

Mode 2

(ns)

Mode 3

(ns)

Mode 4

(ns)

SpecID

Cycle Time

min

600

383

240

180

120

A8.1

Address valid to DIOR/DIOW setup

min

A8.2

DIOR/DIOW pulse width 16-bit

8-bit

min

165

290

125

290

100

290

A8.3

t2i

DIOR/DIOW recovery time

min

—

A8.4

DIOW data setup

min

A8.5

DIOW data hold

min

A8.6

DIOR data setup

min

A8.7

DIOR data hold

min

55555

A8.8

DIOR/DIOW to address

valid hold

min

2015101010

A8.9

IORDY setup

max

A8.10

IORDY pulse width

max

1250

A8.11

MPC5200B датащи(PDF) 29 Page - Freescale Semiconductor, Inc

MPC5200B датащи(HTML) 29 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

датащи скачать

ссылки URL