MPC5200B_10 datasheet(24/72 Pages) FREESCALE

24 / 72 page

MPC5200B Data Sheet, Rev. 4

Freescale Semiconductor

NOTES:

1. ACK can shorten the CS pulse width.

Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified from

0–65535.

2. In Large Flash and MOST Graphics mode the shared PCI/ATA pins, used as address lines, are released at the same moment

as the CS. This can cause the address to change before CS is deasserted.

3. ACK is input and can be used to shorten the CS pulse width.

4. Only available in Large Flash and MOST Graphics mode.

5. Only available in MOST Graphics mode.

6. Deadcycles are only used, if no arbitration to an other module (ATA or PCI) of the shared local bus happens. If arbitration

happens the bus can be driven within 4 IPB clocks by an other modules.

t10

DATA input setup before CS negation

8.5

—ns

—

A7.12

t11

DATA input hold after CS negation

(DC + 1) × tPCIck

(6)

A7.13

t12

ACK assertion after CS assertion

tPCIck

—ns

(3)

A7.14

t13

ACK negation after CS negation

—tPCIck

(3)

A7.15

t14

TS assertion before CS assertion

—6.9

(4)

A7.16

t15

TS pulse width

tPCIck

(4)

A7.17

t16

TSIZ valid before CS assertion

tIPBIck

—ns

(5)

A7.18

t17

TSIZ hold after CS negation

tIPBIck

—ns

(5)

A7.19

t18

ACK change before PCI clock

—2.0

(1)

A7.20

t19

ACK change after PCI clock

—4.4

(1)

A7.21

Table 24. Non-MUXed Mode Timing (continued)

Sym

Description

Min

Max

Units

Notes

SpecID

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