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MPC5200B датащи(PDF) 44 Page - Freescale Semiconductor, Inc

номер детали MPC5200B
подробное описание детали  SDRAM/DDR Memory Controller
PDF  72 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC5200B датащи(HTML) 44 Page - Freescale Semiconductor, Inc

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MPC5200B Data Sheet, Rev. 4
44
Freescale Semiconductor
Figure 34. Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1)
NOTE
Output timing is specified at a nominal 50 pF load.
Table 39. Timing Specifications — SPI Slave Mode, Format 1 (CPHA = 1)
Sym
Description
Min
Max
Units
SpecID
1
Cycle time
4
1024
IP-Bus Cycle(1)
1 Inter Peripheral Clock is defined in the MPC5200B User’s Manual (MPC5200BUM).
A11.31
2
Clock high or low time
2
512
IP-Bus Cycle(1)
A11.32
3
Slave select to clock delay
15.0
—
ns
A11.33
4
Output data valid
—
50.0
ns
A11.34
5
Input Data setup time
50.0
—
ns
A11.35
6
Input Data hold time
0.0
—
ns
A11.36
7
Slave disable lag time
15.0
—
ns
A11.37
8
Sequential Transfer delay
1
—
IP-Bus Cycle(1)
A11.38
SCK
(CLKPOL=0)
SCK
(CLKPOL=1)
MOSI
Output
Output
Output
SS
Output
MISO
Input
1
22
7
8
3
4
6
10
9
9
10
5



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