AS8218 datasheet(64/123 Pages) AMSCO

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Data Sheet AS8218 / AS8228

Revision 3.0, 31-May-06

Page 64 of 123

8.4

Serial Peripheral Interface (SPI)

The Serial Peripheral Interface (SPI) represents a synchronous, bit serial 4-wire interface for full-duplex data

transfer. It’s primarily used here to communicate with an external EEPROM memory, which must fulfil the

requirements described below. The EEPROM is selectable in size from 1kByte to 32kByte in binary steps.

The SPI always operates in master mode, whereas the EEPROM works in slave mode. The bootloader controls

the SPI during system start up. After that it is available to the MCU for free programming.

SPI Signals

Name

Type

Description

Input

Serial input from slave device

Output

Serial output to slave

Output

Clock output to slave device

S_N

Output

Chip select output to slave device (low active)

SPI

Master

EEPROM

S_N

EEP_S_N

EEP_WP_N

EEP_HOLD_N

EEP_SO

EEP_SI

EEP_SC

AS8218/

AS8228

3.3V

Figure 9:

Typical SPI connection to an EEPROM

Many EEPROMs provide a HOLD_N (hold protocol) pin and a WP_N pin (write protect), which must be held ‘1’,

otherwise the operation is blocked.

During startup phase, the bootloader takes control over the SPI and generates the read out sequence

automatically.

Key Features

Standard 4 wire synchronous serial interface (SI, SO, SC, S_N)

Master mode operation only

8-bit word length (variable transmit/receive word optional)

Shift clock SC high when idle

MSB is always transmitted first

Four selectable clocking schemes (clock idle state / clock phase)

Selectable SPI clock rate divider (from mcu_clk/2 to mcu_clk/65536)

Three maskable interrupts (transmission complete, overrun, collision)

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