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AS8218 датащи(PDF) 68 Page - ams AG |
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AS8218 датащи(HTML) 68 Page - ams AG |
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68 / 123 page ![]() Data Sheet AS8218 / AS8228 Revision 3.0, 31-May-06 Page 68 of 123 It is important to note, that the mcu_clk may also be divided down as described under MCUCLKDIV Register (‘mcu_clk’). Therefore the SPI output clock SC is also dependent on the programming of the mcu_clk frequency. Recommended programming for 3.579545MHz mcu clock rate, SPI enabled, SC clock phase = ‘11’, master: Value SC Clock Rate 1.74MHz F0h 0.895MHz F1h 0.447MHz F2h Status Register (SSPSTAT, 9402h) MSB LSB ITRA IOVR ICOL - CSI - - - Bit Symbol Function 7 ITRA 1 Transmission complete interrupt issued. Issued after new data word is available in data-register (slave configuration), or if data-register has been shifted out after write access (master configuration) 6 IOVR 1 Overrun interrupt issued. Issued if ITRA is still set from previous transmission and new data arrives (master and slave configuration) 5 ICOL 1 Write-collision interrupt issued. Issued if data-register is written during receive (slave configuration) or transmit (master configuration) 4 - Not used 3 CSI Always ‘0’, has no effect 2 - Not used 1 - Not used 0 - Not used Note: 1) Flag-bits change state independent of the state of the corresponding interrupt-enable bit of the control register. |
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