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AS8218 датащи(PDF) 71 Page - ams AG |
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AS8218 датащи(HTML) 71 Page - ams AG |
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71 / 123 page ![]() Data Sheet AS8218 / AS8228 Revision 3.0, 31-May-06 Page 71 of 123 BP1, BP0 allows the selection of one out of 4 protection schemes. In order to protect against inadvertent programming the user can see these bits. Please note that the protected range of EEPROM cannot be overwritten via an SCT command there anymore. Reprogramming must be done with a dedicated program then. Instruction Set There must be at least 4 instructions with the coding shown in the table for they are deployed by the bootloader to download the user program and by the SCT unit to upload the user program to the EEPROM. Instruction Name Instruction Format Description READ 03h Read data from memory starting with selected address WRITE 02h Write data to memory beginning at selected address. Most EEPROMs allow page writing of pages 16, 32, 64 or even more bytes for faster device programming. Before every page write operation a WREN instruction must be applied – see also bootloading and uploading sequence for details. WREN 06h Write enable EEPROM, enables write operation RDSR 05h Read EEPROM Status register, bit 0 = WIP required for AS8218 / AS8228 SPI Modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: - CPOL = 0, CPHA = 0 - CPOL = 1, CPHA = 1 (It is recommended to set CPOL = 1, CPHA = 1 in your program: The build-in bootloader uses this setting as well.) For these two modes, input data is latched in on the rising edge of Serial Clock (SC), and output data is issued on the falling edge of Serial Clock (SC). The recommended mode is shown in Figure 12. The clock polarity SC is ‘1’ when the bus master is in Stand-by mode and not transferring data (idle state): - SC remains at 1 for (CPOL = 1, CPHA = 1) Figure 12: SPI modes recommended EEP_SC(in) EEP_SI(in) EEP_SO(out ) 1 1 |
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