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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AS8218 датащи(PDF) 66 Page - ams AG |
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AS8218 датащи(HTML) 66 Page - ams AG |
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66 / 123 page  Data Sheet AS8218 / AS8228 Revision 3.0, 31-May-06 Page 66 of 123 Control Register (SSPCON, 9400h) The control register is used for enabling the SPI-interrupts and to control the chip select of the SPI. MSB LSB IETR IEOV IECO IECS CSO - AUTO - Bit Symbol Function 7 IETR Transmit interrupt enable Issued after data register has been serially loaded with new data (slave mode) or if data has been shifted out after write access (master mode) 0: disable 1: enable 6 IEOV Overrun interrupt enable Issued if ITRA still set and new data serially arrived 0: disable 1: enable 5 IECO Write collision interrupt enable Issued if data register is written during transmission 0: disable 1: enable 4 IECS Chip select interrupt enable Issued if chip-select pin is activated during master/slave mode 0: disable 1: enable 3 CSO Chip select output state in master mode if AUTO = 0 Inverted state of output signal S_N 0: S_N = ‘1’ 1: S_N = ‘0’ (active) 2 - Not used 1 AUTO 1: Automatically activates the S_N (= ’0’) after data has been written to the data register and deactivates S_N (= ’1’) after transfer completed 0: S_N depends on the CSO bit ( → manual S_N setting) 0 - Not used Recommended programming for SSPCON with no interrupts enabled: Mode SSPCON S_N Auto mode 02h Manual S_N=1 (inactive) 00h Manual S_N=0 (active) 08h |
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