AS8218 datasheet(67/123 Pages) AMSCO

67 / 123 page

Data Sheet AS8218 / AS8228

Revision 3.0, 31-May-06

Page 67 of 123

Clock Divider Register (SSPCLKDIV, 9401h)

The clock divider register contains control bits to configure the clock-divider, to set-up the serial-clock SC, to

enable the SPI and to select master or slave mode.

MSB

LSB

ENBL

CIDLE

CPHA

M/S

CLKDIV.3

CLKDIV.2

CLKDIV.1

CLKDIV.0

Bit

Symbol

Function

ENBL

SPI enable. Enables the SPI interface

1: enable

0: disable

CIDLE

Bit6

CPHA

Bit5

SC Idle

Data shifted

out on SC

Input sampled

on SC

falling

rising

falling

CIDLE

Serial clock SC idle state

1: SC idles high

0: SC idles low

rising

falling

rising

CPHA

Serial clock SC phase

Data is samples and shifted out

according to CIDLE/CPHA

Note: The CIDLE/CPHA set at 1 1 is used internally by most

standard available EEPROMs

M/S

Master/Slave mode

1: Master mode, must be ‘1’

0: Slave mode (stops SPI operation), there is no slave mode available

Bit3

Bit2

Bit1

Bit0

SC-Rate

1 : 2

1 : 4

1 : 8

CLKDIV.3

1 : 16

1 : 32

1 : 64

1 : 128

CLKDIV.2

1 : 256

1 : 512

1 : 1,024

1 : 2,048

CLKDIV.1

1 : 4,096

1 : 8,192

1 : 16,384

1 : 32,768

CLKDIV.0

Clock divider exponent

In master mode, SPI output clock SC is

MCU_CLK / 2

CLKDIV+1

1 : 65,536

The SPI output clock SC, which is derived from the mcu clock (mcu_clk) may be divided down as shown in the

table above.

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