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MPC5121E датащи(PDF) 57 Page - Freescale Semiconductor, Inc

номер детали MPC5121E
подробное описание детали  e300 Power Architecture processor core
PDF  86 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC5121E датащи(HTML) 57 Page - Freescale Semiconductor, Inc

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Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 4
Freescale Semiconductor
57
Figure 35. Ethernet Timing Diagram – MII Rx Signal
Figure 36. Ethernet Timing Diagram – MII Tx Signal
Figure 37. Ethernet Timing Diagram – MII Async
Table 32. MII Tx Signal Timing
Sym
Description
Min
Max
Unit
SpecID
5
TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER
invalid
3
—
ns
A11.5
6
TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER valid
—
25
ns
A11.6
7
TX_CLK pulse width high
35%
65%
TX_CLK Period1
1 The TX_CLK frequency shall be 25% of the nominal transmit frequency, e.g., a PHY operating at 100 Mb/s must provide
a TX_CLK frequency of 25 MHz and a PHY operating at 10 Mb/s must provide a TX_CLK frequency of 2.5 MHz. See
the IEEE 802.3 Specification.
A11.7
8
TX_CLK pulse width low
35%
65%
TX_CLK Period1
A11.8
Table 33. MII Async Signal Timing
Sym
Description
Min
Max
Unit
SpecID
9
CRS, COL minimum pulse width
1.5
—
TX_CLK Period
A11.9
RX_CLK (Input)
RXD[3:0] (inputs)
RX_DV
RX_ER
1
2
3
4
TX_CLK (Input)
TXD[3:0] (Outputs)
TX_EN
TX_ER
5
6
7
8
CRS, COL
9



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