MPC5121E datasheet(32/86 Pages) FREESCALE

32 / 86 page

MPC5121E/MPC5123 Data Sheet, Rev. 4

Electrical and Thermal Characteristics

Freescale Semiconductor

3.3.4

External Interrupts

The MPC5121e/MPC5123 provides three different kinds of external interrupts:

•

IRQ interrupts

•

GPIO interrupts with simple interrupt capability (not available in power-down mode)

•

WakeUp interrupts

IPIC inputs must be valid for at least tPICWID to ensure proper operation in edge triggered mode.

3.3.5

SDRAM (DDR)

The MPC5121e/MPC5123 memory controller supports three types of DDR devices:

•

DDR-1 (SSTL_2 class II interface)

•

DDR-2 (SSTL_18 interface)

•

LPDDR/Mobile-DDR (1.8V I/O supply voltage)

JEDEC standards define the minimum set of requirements for complient memory devices:

— JEDEC STANDARD, DDR2 SDRAM SPECIFICATION, JESD79-2C, MAY 2006

— JEDEC STANDARD, Double Data Rate (DDR) SDRAM Specification, JESD79E, May 2005

— JEDEC STANDARD, Low Power Double Data Rate (LPDDR) SDRAM Specification, JESD79-4, May 2006

The MPC5121e/MPC5123 supports the configuration of two output drive strengths for DDR2 and LPDDR:

•

Full drive strength

•

Half drive strengh (intended for ligther loads or point-to-point environments)

The MPC5121e/MPC5123 memory controller supports dynamic on-die termination in the host device and in the DDR2 memory

device.

This section includes AC specifications for all DDR SDRAM pins. The DC parameters are specified in the DC Electrical

Characteristics.

tS_POR_CONF

Reset configuration setup time before assertion of PORESET

1 cycle

A3.14

tH_POR_CONF

Reset configuration hold time after assertion of PORESET

1 cycle

A3.15

tHR_SR_DELAY

Time from falling edge of HRESET to falling edge of SRESET

4 cycles

A3.16

tHRHOLD

Time HRESET must be held low before a qualified reset occurs

4 cycles

A3.17

tSRHOLD

Time SRESET must be held low before a qualified reset occurs

4 cycles

A3.18

tSRMIN

Time SRESET is asserted after it has been qualified

1 cycles

A3.19

Table 19. IPIC Input AC Timing Specifications1

1 T is the IP bus clock cycle. T = 12 ns is the minimum value (for the maximum IP bus freqency

of 83 MHz).

Description

Symbol

Min

Unit

SpecID

IPIC inputs—minimum pulse witdh

tPICWID

A4.1

Table 18. Reset Timing (continued)

Symbol

Description

Value

SYS_XTALI

SpecID

MPC5121E датащи(PDF) 32 Page - Freescale Semiconductor, Inc

MPC5121E датащи(HTML) 32 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

датащи скачать

ссылки URL