MPC5121E datasheet(45/86 Pages) FREESCALE

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Electrical and Thermal Characteristics

MPC5121E/MPC5123 Data Sheet, Rev. 4

Freescale Semiconductor

3.3.9

PATA

The MPC5121e/MPC5123 ATA Controller (PATA) is completely software programmable. It can be programmed to operate

with ATA protocols using their respective timing, as described in the ANSI ATA-4 specification. The ATA interface is

completely asynchronous in nature. Signal relationships are based on specific fixed timing in terms of timing units

(nanoseconds).

ATA data setup and hold times, with respect to Read/Write strobes, are software programmable inside the ATA Controller. Data

setup and hold times are implemented using counters. The counters count the number of ATA clock cycles needed to meet the

ANSI ATA-4 timing specifications. For details, see the ANSI ATA-4 specification and how to program an ATA Controller and

ATA drive for different ATA protocols and their respective timing. See the MPC5121e Microcontroller Reference Manual.

The MPC5121e/MPC5123 ATA Host Controller design makes data available coincidentally with the active edge of the WRITE

strobe in PIO and Multiword DMA modes.

•

Write data is latched by the drive at the inactive edge of the WRITE strobe. This gives ample setup-time beyond that

required by the ATA-4 specification.

•

Data is held unchanged until the next active edge of the WRITE strobe. This gives ample hold-time beyond that

required by the ATA-4 specification.

All ATA transfers are programmed in terms of system clock cycles (IP bus clocks) in the ATA Host Controller timing registers.

This puts constraints on the ATA protocols and their respective timing modes in which the ATA Controller can communicate

with the drive.

Faster ATA modes (i.e., UDMA 0, 1, 2 ) are supported when the system is running at a sufficient frequency to provide adequate

data transfer rates. Adequate data transfer rates are a function of the following:

•

The MPC5121e/MPC5123 operating frequency (IP bus clock frequency)

•

Internal MPC5121e/MPC5123 bus latencies

•

Other system load dependent variables

tCS

NFC_WP Pulse Width

T – 1

—

A8.5

tCS

NFC_ALE Setup Time

T – 1

—

A8.6

tCS

NFC_ALE Hold Time

T – 1

—

A8.7

tCS

Data Setup Time

T – 2

—

A8.8

tCS

Data Hold Time

T – 1

—

A8.9

tCS

Write Cycle Time

—

A8.10

tCS

NFC_WE Hold Time

T – 1

—

A8.11

tCS

Ready to NFC_RE Low

5T + 2

—

A8.12

tCS

NFC_RE Pulse Width

1.5T – 1

—

A8.13

tCS

READ Cycle Time

—

A8.14

tCS

NFC_RE High Hold Time

0.5T

—

A8.15

1 T is the flash clock cycle.

T = 45 ns, frequency = 22 MHz (boot configuration, IP bus = 66 MHz)

T = 36 ns, frequency = 27 MHz (maximum configurable frequency, IP bus = 83 MHz)

Table 24. NFC Timing Characteristics1 (continued)

Timing

parameter

Description

Min. value

Max. value

Unit

SpecID

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