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MPC5121E датащи(PDF) 37 Page - Freescale Semiconductor, Inc

номер детали MPC5121E
подробное описание детали  e300 Power Architecture processor core
PDF  86 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC5121E датащи(HTML) 37 Page - Freescale Semiconductor, Inc

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Electrical and Thermal Characteristics
MPC5121E/MPC5123 Data Sheet, Rev. 4
Freescale Semiconductor
37
t14
Write Burst ACK assertion after CS[x]
assertion
(2.5 +WS) ×tLPCck –tOD
(2.5 +WS) ×tLPCck +tOD
ns
A7.15
t15
Write Burst DATA valid
tLPCck –tOD
—
ns
A7.16
t16
Non-MUXed Mode: asynchronous write
Burst ADDR valid before write DATA
valid
0.5 × tLPCck –tOD
0.5 × tLPCck +tOD
ns
A7.17
t17
MUXed Mode: ADDR cycle
AL × 2 × tLPCck –tOD
AL ×2×tLPCck
ns
A7.18
t18
MUXed Mode: ALE cycle
AL × tLPCck
AL × tLPCck
ns
A7.19
t19
Non-MUXed Mode Page Burst: ADDR
cycle
tLPCck –tOD
tLPCck
ns
A7.20
t20
Non-MUXed Mode Page Burst: Burst
DATA (rd) input setup before next ADDR
cycle
tOD +t6
—
ns
A7.21
t21
Non-MUXed Mode Page Burst: Burst
DATA (rd) input hold after next ADDR
cycle
0
—
ns
A7.22
t22
MUXed Mode: non-Burst CS[x] pulse
width
(ALT ×(AL ×2)+2+WS)
×tLPCck
(ALT × (AL × 2) + 2 + WS)
×tLPCck
ns
A7.23
t23
MUXed Mode: read Burst CS[x] pulse
width
[ALT (AL× 2) +2+WS
+ BBT/DS] × tLPCck
[ALT ×(AL ×2)+2+WS
+BBT/DS] × tLPCck
ns
A7.24
t24
MUXed Mode: write Burst CS[x] pulse
width
[ALT × (AL × 2) + 2.5 + WS
+ BBT/DS] × tLPCck
[ALT ×(AL ×2)+2.5+WS
+BBT/DS] × tLPCck
ns
A7.25
Table 23. LPC Timing (continued)
Sym
Description
Min
Max
Units
SpecID



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