MPC5121E datasheet(22/86 Pages) FREESCALE

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MPC5121E/MPC5123 Data Sheet, Rev. 4

Electrical and Thermal Characteristics

Freescale Semiconductor

Notes:

1. General IO – Rise and Fall Times at Drive load 50pF.

2. PCI – Rise and Fall Times at Drive load 10pF.

3. DDR – for LPDDR/Mobile-DDR, slew rate is measured between 20% of VDD_MEM_IO and 80% of VDD_MEM_IO.

4. DDR – for DDR, DDR2, rising signals, slew rate is measured between VDD_MEM_IO × 0.5 and ViHAC. For falling signals, slew

rate is measured between VDD_MEM_IO × 0.5 and ViLAC.

5. DDR – Rise and Fall Times terminated at the destination with 50 ohm to MVTT (0.5 × VDD_MEM_IO), with 4 pF representing the

DDR input capacitance.

7 See Table 7 for the typical drive capability of a specific signal pin based on the type of output driver associated with that pin

as listed in Table 3.

8 All injection current is transferred to V

DD_IO/VDD_MEM_IO. An external load is required to dissipate this current to maintain the

power supply within the specified voltage range.

Total injection current for all digital input-only and all digital input/output pins must not exceed 10 mA. Exceeding this limit can

cause disruption of normal operation.

Table 7. I/O Pads—Drive Current, Slew Rate

Pad Type

Supply Voltage

Drive Select/Slew

Rate Control

Rise time

max (ns)

Fall time

max (ns)

Current

Ioh (mA)

Current

Iol (mA)

SpecID

General IO

VDD_IO = 3.3V

configuration 3 (11)

1.4

1.6

D3.41

configuration 2 (10)

9.8

D3.42

configuration 1 (01)

D3.43

configuration 0 (00)

140

183

D3.44

DDR

VDD_MEM_IO = 2.5V (DDR)

configuration 3 (011)

16.2

D3.45

VDD_MEM_IO = 1.8V (LPDDR) configuration 0 (000)

4.6

D3.46

configuration 1 (001)

8.1

D3.47

VDD_MEM_IO = 1.8V (DDR2) configuration 2 (010)

5.3

D3.48

configuration 6 (110)

13.4

D3.49

PCI

VDD_IO = 3.3V

configuration 1 (1)

1.4

D3.50

configuration 0 (0)

D3.51

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