ATmega16A datasheet(87/352 Pages) ATMEL

87 / 352 page

8154B–AVR–07/09

ATmega16A

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles

from an edge has been applied to the T1/T0 pin to the counter is updated.

Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least

one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

Each half period of the external clock applied must be longer than one system clock cycle to

ensure correct sampling. The external clock must be guaranteed to have less than half the sys-

tem clock frequency (f

ExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses

sampling, the maximum frequency of an external clock it can detect is half the sampling fre-

quency (Nyquist sampling theorem). However, due to variation of the system clock frequency

and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is

recommended that maximum frequency of an external clock source is less than f

clk_I/O/2.5.

An external clock source can not be prescaled.

Figure 15-2. Prescaler for Timer/Counter0 and Timer/Counter1

(1)

Note:

1. The synchronization logic on the input pins (

T1/T0) is shown in Figure 15-1.

15.5

15.5.1

SFIOR – Special Function IO Register

• Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0

When this bit is written to one, the Timer/Counter1 and Timer/Counter0 prescaler will be reset.

The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will

have no effect. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a

reset of this prescaler will affect both timers. This bit will always be read as zero.

PSR10

Clear

clk

I/O

Synchronization

Bit

ADTS2

ADTS1

ADTS0

–

ACME

PUD

PSR2

PSR10

SFIOR

Read/Write

R/W

Initial Value

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