ATmega16A datasheet(84/352 Pages) ATMEL

84 / 352 page

8154B–AVR–07/09

ATmega16A

Note:

1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the compare

match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page

78 for more details.

• Bit 2:0 – CS02:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter.

If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the

counter even if the pin is configured as an output. This feature allows software control of the

counting.

14.9.2

TCNT0 – Timer/Counter Register

The Timer/Counter Register gives direct access, both for read and write operations, to the

Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the compare

match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,

introduces a risk of missing a compare match between TCNT0 and the OCR0 Register.

Table 14-5.

Compare Output Mode, Phase Correct PWM Mode(1)

COM01

COM00

Description

Normal port operation, OC0 disconnected.

Reserved

Clear OC0 on compare match when up-counting. Set OC0 on compare match

when downcounting.

Set OC0 on compare match when up-counting. Clear OC0 on compare match

when downcounting.

Table 14-6.

Clock Select Bit Description

CS02

CS01

CS00

Description

No clock source (Timer/Counter stopped).

clk

I/O/(No prescaling)

clk

I/O/8 (From prescaler)

clk

I/O/64 (From prescaler)

clk

I/O/256 (From prescaler)

clk

I/O/1024 (From prescaler)

External clock source on T0 pin. Clock on falling edge.

External clock source on T0 pin. Clock on rising edge.

Bit

765

432

TCNT0[7:0]

TCNT0

Read/Write

R/W

Initial Value

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