ATmega16A datasheet(68/352 Pages) ATMEL

68 / 352 page

8154B–AVR–07/09

ATmega16A

low level interrupt is selected, the low level must be held until the completion of the currently

executing instruction to generate an interrupt.

• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-

sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the

interrupt are defined in Table 13-2. The value on the INT0 pin is sampled before detecting

edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will

generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level

interrupt is selected, the low level must be held until the completion of the currently executing

instruction to generate an interrupt.

13.1.2

MCUCSR – MCU Control and Status Register

• Bit 6 – ISC2: Interrupt Sense Control 2

The Asynchronous External Interrupt 2 is activated by the external pin INT2 if the SREG I-bit and

the corresponding interrupt mask in GICR are set. If ISC2 is written to zero, a falling edge on

INT2 activates the interrupt. If ISC2 is written to one, a rising edge on INT2 activates the inter-

rupt. Edges on INT2 are registered asynchronously. Pulses on INT2 wider than the minimum

pulse width given in “External Interrupts Characteristics” on page 297 will generate an interrupt.

Shorter pulses are not guaranteed to generate an interrupt. When changing the ISC2 bit, an

interrupt can occur. Therefore, it is recommended to first disable INT2 by clearing its Interrupt

Enable bit in the GICR Register. Then, the ISC2 bit can be changed. Finally, the INT2 Interrupt

Flag should be cleared by writing a logical one to its Interrupt Flag bit (INTF2) in the GIFR Reg-

ister before the interrupt is re-enabled.

Table 13-1.

Interrupt 1 Sense Control

ISC11

ISC10

Description

The low level of INT1 generates an interrupt request.

Any logical change on INT1 generates an interrupt request.

The falling edge of INT1 generates an interrupt request.

The rising edge of INT1 generates an interrupt request.

Table 13-2.

Interrupt 0 Sense Control

ISC01

ISC00

Description

The low level of INT0 generates an interrupt request.

Any logical change on INT0 generates an interrupt request.

The falling edge of INT0 generates an interrupt request.

The rising edge of INT0 generates an interrupt request.

Bit

6543

210

JTD

ISC2

–

JTRF

WDRF

BORF

EXTRF

PORF

MCUCSR

Read/Write

R/W

Initial Value

See Bit Description

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