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ATmega16A датащи(PDF) 65 Page - ATMEL Corporation |
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ATmega16A датащи(HTML) 65 Page - ATMEL Corporation |
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65 / 352 page ![]() 65 8154B–AVR–07/09 ATmega16A 12.4 Register Description 12.4.1 SFIOR – Special Function I/O Register • Bit 2 – PUD: Pull-up disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Con- figuring the Pin” on page 50 for more details about this feature. 12.4.2 PORTA – Port A Data Register 12.4.3 DDRA – Port A Data Direction Register 12.4.4 PINA – Port A Input Pins Address 12.4.5 PORTB – Port B Data Register 12.4.6 DDRB – Port B Data Direction Register Bit 7 6 5 4 3 2 1 0 ADTS2 ADTS1 ADTS0 – ACME PUD PSR2 PSR10 SFIOR Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 543 210 PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 PORTA Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 765 432 10 DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 765 432 10 PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 PINA Read/Write RR RRR RRR Initial Value N/A N/A N/A N/A N/A N/A N/A N/A Bit 765 432 10 PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 543 210 DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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