STM32W108HB datasheet(35/179 Pages) STMICROELECTRONICS

35 / 179 page

STM32W108CB, STM32W108HB

System modules

Doc ID 16252 Rev 2

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5.2

Resets

The STM32W108 resets are generated from a number of sources. Each of these reset

sources feeds into central reset detection logic that causes various parts of the system to be

reset depending on the state of the system and the nature of the reset event.

5.2.1

Reset sources

For power-on reset (POR HV and POR LV) thresholds, see Section 12.3.2: Operating

conditions at power-up on page 159.

Watchdog reset

The STM32W108 contains a watchdog timer (see also the Watchdog Timer section) that is

clocked by the internal 1 kHz timing reference. When the timer expires it generates the reset

source WATCHDOG_RESET to the Reset Generation module.

Software reset

The ARM® Cortex-M3 CPU can initiate a reset under software control. This is indicated with

the reset source SYSRESETREQ to the Reset Generation module.

Option byte error

The flash memory controller contains a state machine that reads configuration information

from the information blocks in the Flash at system start time. An error check is performed on

the option bytes that are read from Flash and, if the check fails, an error is signaled that

provides the reset source OPT_BYTE_ERROR to the Reset Generation module.

If an option byte error is detected, the system restarts and the read and check process is

repeated. If the error is detected again the process is repeated but stops on the 3rd failure.

The system is then placed into an emulated deep sleep where recovery is possible. In this

state, Flash memory readout protection is forced active to prevent secure applications from

being compromised.

Debug reset

The Serial Wire/JTAG Interface (SWJ) provides access to the SWJ Debug Port (SWJ-DP)

registers. By setting the register bit CDBGRSTREQ in the SWJ-DP, the reset source

CDBGRSTREQ is provided to the Reset Generation module.

JRST

One of the STM32W108's pins can function as the JTAG reset, conforming to the

requirements of the JTAG standard. This input acts independently of all other reset sources

and, when asserted, does not reset any on-chip hardware except for the JTAG TAP. If the

STM32W108 is in the Serial Wire mode or if the SWJ is disabled, this input has no effect.

Deep sleep reset

The Power Management module informs the Reset Generation module of entry into and exit

from the deep sleep states. The deep sleep reset is applied in the following states: before

entry into deep sleep, while removing power from the memory and core domain, while in

deep sleep, while waking from deep sleep, and while reapplying power until reliable power

levels have been detect by POR LV.

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