STM32W108HB datasheet(83/179 Pages) STMICROELECTRONICS

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STM32W108CB, STM32W108HB

General-purpose timers

Doc ID 16252 Rev 2

83/179

Note:

When the STM32W108 enters debug mode and the ARM® Cortex-M3 core is halted, the

counters continue to run normally.

Prescaler

The prescaler can divide the counter clock frequency by power of two from 1 through 32768.

It is based on a 16-bit counter controlled through the 4-bit TIM_PSCEXP bit field in the

TIMx_PSC register. The factor by which the counter is divided is two raised to the power

TIM_PSCEXP (2TIM_PSCEXP).

It can be changed on the fly as this control register is buffered. The new prescaler ratio is

used starting at the next update event.

Figure 11 gives an example of the counter behavior when the prescaler ratio is changed on

the fly.

Figure 11.

Counter timing diagram with prescaler division change from 1 to 4

8.1.2

Counter modes

Up-counting mode

In up-counting mode, the counter counts from 0 to the auto-reload value (contents of the

TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

An update event can be generated at each counter overflow, by setting the TIM_UG bit in

the TIMx_EGR register, or by using the slave mode controller.

Software can disable the update event by setting the TIM_UDIS bit in the TIMx_CR1

registers. No update event will occur until the TIM_UDIS bit is written to 0. Both the counter

and the prescalar counter restart from 0, but the prescale rate does not change. In addition,

if the TIM_URS bit in the TIMx_CR1 register is set, setting the TIM_UG bit generates an

update event but without setting the INT_TIMUIF flag. Thus no interrupt request is sent. This

avoids generating both update and capture interrupts when clearing the counter on the

capture event.

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