PCF8534AHLSLASH1 datasheet(8/47 Pages) NXP

8 / 47 page

PCF8534A_5

Product data sheet

Rev. 05 — 6 August 2009

8 of 47

NXP Semiconductors

PCF8534A

Universal LCD driver for low multiplex rates

The host microprocessor or microcontroller maintains the 2-line I2C-bus communication

channel with the PCF8534A.

Biasing voltages for the multiplexed LCD waveforms are generated internally, removing

the need for an external bias generator. The internal oscillator is selected by connecting

pin OSC to VSS. The only other connections required to complete the system are the

power supplies (pins VDD, VSS and VLCD) and the LCD panel selected for the application.

7.1 Power-on reset

At power-on the PCF8534A resets to a default starting condition:

• All backplane outputs are set to VLCD

• All segment outputs are set to VLCD

• The selected drive mode is: 1:4 multiplex with 1

⁄

3 bias

• Blinking is switched off

• Input and output bank selectors are reset

• The I2C-bus interface is initialized

• The data pointer and the subaddress counter are cleared (set to logic 0)

• The display is disabled

Do not transfer data on the I2C-bus after a power-on for at least 1 ms to allow the reset

action to complete.

7.2 LCD bias generator

Fractional LCD biasing voltages are obtained from an internal voltage divider of three

series resistors connected between pins VLCD and VSS. The center resistor is switched out

of the circuit to provide the 1

⁄

2 bias voltage level for the 1:2 multiplex conﬁguration.

7.3 LCD voltage selector

The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the

selected LCD drive conﬁguration. The operation of the voltage selector is controlled by the

mode-set command (see Table 10) from the command decoder. The biasing

Fig 5.

Typical system conﬁguration

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

2Cb

SDA

SCL

OSC

60 segment drives

4 backplanes

LCD PANEL

(up to 240

elements)

PCF8534A

SA0

VDD

VSS

VDD

VLCD

001aah616

≤

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