PCF8534AHLSLASH1 datasheet(23/47 Pages) NXP

23 / 47 page

PCF8534A_5

Product data sheet

Rev. 05 — 6 August 2009

23 of 47

NXP Semiconductors

PCF8534A

Universal LCD driver for low multiplex rates

8.1.3 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge

cycle.

• A slave receiver which is addressed must generate an acknowledge after the

reception of each byte.

• A master receiver must generate an acknowledge after the reception of each byte that

has been clocked out of the slave transmitter.

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be taken into

consideration).

• A master receiver must signal an end-of-data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

master receiver must leave the data line HIGH during the 9th pulse to not

acknowledge. The master will now generate a STOP condition.

Acknowledgement on the I2C-bus is illustrated in Figure 16.

8.1.4 PCF8534A I2C-bus controller

The PCF8534A acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or

transmit data to an I2C-bus master receiver. The only data output from the PCF8534A are

the acknowledge signals of the selected devices. Device selection depends on the

I2C-bus slave address, the transferred command data and the hardware subaddress.

In single device application, the hardware subaddress inputs A0, A1 and A2 are normally

tied to VSS which deﬁnes the hardware subaddress 0. In multiple device applications

A0, A1 and A2 are tied to VSS or VDD using a binary coding scheme so that no two

devices with a common I2C-bus slave address have the same hardware subaddress.

8.1.5 Input ﬁlters

To enhance noise immunity in electrically adverse environments, RC low-pass ﬁlters are

provided on the SDA and SCL lines.

Fig 16. Acknowledgement of the I2C-bus

mbc602

START

condition

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from

master

PCF8534AHL/1 датащи(PDF) 23 Page - NXP Semiconductors

PCF8534AHL/1 датащи(HTML) 23 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

датащи скачать

ссылки URL