PCF8534AHLSLASH1 datasheet(21/47 Pages) NXP

21 / 47 page

PCF8534A_5

Product data sheet

Rev. 05 — 6 August 2009

21 of 47

NXP Semiconductors

PCF8534A

Universal LCD driver for low multiplex rates

7.15 Blinker

The display blinking capabilities of the PCF8534A are very versatile. The whole display

can be blinked at frequencies set by the blink select command (see Table 14). The

blinking frequencies are fractions of the clock frequency. The ratios between the clock and

blinking frequencies depend on the mode in which the device is operating (see Table 7).

An additional feature is for the arbitrary selection of LCD segments to be blinked. This

applies to the static and 1:2 multiplex drive modes and is implemented without any

communication overheads. Using the output bank selector, the displayed RAM banks are

exchanged with alternate RAM banks at the blinking frequency. This mode can also be

speciﬁed by the blink select command.

In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of

LCD segments can be blinked by selectively changing the display RAM data at ﬁxed time

intervals.

If the entire display needs to be blinked at a frequency other than the nominal blinking

frequency, this can be done using the mode set command to set and reset the display

enable bit E at the required rate (see Table 10).

Basic architecture

8.1 Characteristics of the I2C-bus

The I2C-bus provides bidirectional, two-line communication between different ICs or

modules. The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). When

connected to the output stages of a device, both lines must be connected to a positive

supply via a pull-up resistor. Data transfer is initiated only when the bus is not busy.

8.1.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse. Changes in the data line at this time will

be interpreted as a control signal. Bit transfer is illustrated in Figure 13.

Table 7.

Blink frequencies

Assuming that fclk = 1536 Hz.

Blink mode

Operating mode ratio

Blink frequency

Off

Blinking off

2 Hz

1 Hz

0.5 Hz

blink

clk

768

---------

blink

clk

1536

------------

blink

clk

3072

------------

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