PCF8534AHLSLASH1 datasheet(31/47 Pages) NXP

31 / 47 page

PCF8534A_5

Product data sheet

Rev. 05 — 6 August 2009

31 of 47

NXP Semiconductors

PCF8534A

Universal LCD driver for low multiplex rates

12. Dynamic characteristics

[1]

Typical output (duty cycle

δ = 50 %).

[2]

All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an

input voltage swing of VSS to VDD.

Table 17.

Dynamic characteristics

VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Clock

Internal: output pin CLK

fosc

oscillator frequency

VDD = 5 V

[1] 960

1536

3046

External: input pin CLK

fclk(ext)

external clock frequency

VDD = 5 V

797

1536

3046

tclk(H)

HIGH-level clock time

130

µs

tclk(L)

LOW-level clock time

130

µs

Synchronization: input pin SYNC

tPD(SYNC_N)

SYNC propagation delay

tSYNC_NL

SYNC LOW time

µs

Outputs: pins BP0 to BP3 and S0 to S59

tPD(drv)

driver propagation delay

VLCD = 5 V

µs

I2C-bus: timing[2]

Pin SCL

fSCL

SCL frequency

400

kHz

tLOW

LOW period of the SCL clock

1.3

µs

tHIGH

HIGH period of the SCL clock

0.6

µs

Pin SDA

tSU;DAT

data set-up time

100

tHD;DAT

data hold time

Pins SCL and SDA

tBUF

bus free time between a STOP and

START condition

1.3

µs

tSU;STO

set-up time for STOP condition

0.6

µs

tHD;STA

hold time (repeated) START condition

0.6

µs

tSU;STA

set-up time for a repeated START

condition

0.6

µs

rise time of both SDA and SCL signals

0.3

µs

fall time of both SDA and SCL signals

0.3

µs

capacitive load for each bus line

400

tw(spike)

spike pulse width

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