PCF8534AHLSLASH1 datasheet(17/47 Pages) NXP

17 / 47 page

PCF8534A_5

Product data sheet

Rev. 05 — 6 August 2009

17 of 47

NXP Semiconductors

PCF8534A

Universal LCD driver for low multiplex rates

7.9 Backplane outputs

The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane

output signals are generated based on the selected LCD drive mode.

• In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.

If less than four backplane outputs are required the unused outputs can be left as an

open-circuit.

• In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, therefore these two

adjacent outputs can be tied together to give enhanced drive capabilities.

• In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same

signals and can also be paired to increase the drive capabilities.

• In static drive mode: the same signal is carried by all four backplane outputs and they

can be connected in parallel for very high drive requirements.

7.10 Display RAM

The display RAM is a static 60

× 4-bit RAM which stores LCD data. Logic 1 in the RAM bit

map indicates the on-state of the corresponding LCD segment, logic 0 indicates the

off-state. There is a direct relationship between RAM addresses and the segment outputs

and the individual bits of a RAM word and the backplane outputs. The ﬁrst RAM row

corresponds to the 60 segments operated with respect to backplane BP0 (see Figure 11).

In multiplexed LCD applications, the segment data of rows 1 to 4 of the display RAM are

time-multiplexed with BP0, BP1, BP2 and BP3, respectively.

When display data is transmitted to the PCF8534A, the display bytes received are stored

in the display RAM based on the selected LCD drive mode. Data is stored as it arrives and

does not wait for the acknowledge cycle. Depending on the current multiplex mode data is

stored singularly, in pairs, triplets or quadruplets. An example of a 7-segment numeric

display illustrating the storage order for all drive modes is shown in Figure 12. The RAM

storage organization applies equally to other LCD types.

Display RAM bit map showing the direct relationship between backplane outputs, display RAM

addresses and segment outputs and between bits in a RAM word and backplane outputs.

Fig 11. Display RAM bit map

display RAM addresses (columns)/segment outputs (S)

display RAM bits

(rows)/

backplane outputs

(BP)

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