PCF8534AHLSLASH1 datasheet(18/47 Pages) NXP

18 / 47 page

PCF8534A_5

Product data sheet

Rev. 05 — 6 August 2009

18 of 47

NXP Semiconductors

PCF8534A

Universal LCD driver for low multiplex rates

The following applies to Figure 12:

• Static mode: the eight transmitted data bits are placed in row 0 to eight successive

display RAM addresses.

• 1:2 multiplex mode: the eight transmitted data bits are placed in row 0 and 1 to four

successive display RAM addresses.

• 1:3 multiplex mode: the eight transmitted data bits are placed in row 0, 1 and 2 to

three successive addresses. However, bit 2 of the third address is left unchanged.

This last bit can, if necessary, be controlled by an additional transfer to this address

but avoid overriding adjacent data because full bytes are always transmitted.

• 1:4 multiplex mode: the eight transmitted data bits are placed in row 0, 1, 2 and 3 to

two successive display RAM addresses.

7.11 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer. This

allows the loading of an individual display data byte or a series of display data bytes, into

any location of the display RAM. The sequence commences with the initialization of the

data pointer by the load data pointer command. After this, the data byte is stored starting

at the display RAM address indicated by the data pointer (see Figure 12). Once each byte

is stored, the data pointer is automatically incremented based on the selected LCD

conﬁguration.

The contents of the data pointer are incremented as follows:

• In static drive mode by eight.

• In 1:2 multiplex drive mode by four.

• In 1:3 multiplex drive mode by three.

• In 1:4 multiplex drive mode by two.

If an I2C-bus data access terminates early, the state of the data pointer is unknown.

Consequently, the data pointer must be rewritten prior to further RAM accesses.

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