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PCF8534AHL/1 датащи(PDF) 33 Page - NXP Semiconductors |
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PCF8534AHL/1 датащи(HTML) 33 Page - NXP Semiconductors |
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33 / 47 page ![]() PCF8534A_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 6 August 2009 33 of 47 NXP Semiconductors PCF8534A Universal LCD driver for low multiplex rates 13. Application information 13.1 Cascaded operation Large display configurations of up to 16 PCF8534As can be recognized on the same I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable I2C-bus slave address (SA0). If cascaded PCF8534As are synchronized, they can share the backplane signals from one of the devices in the cascade. This is cost-effective in large LCD applications because the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. The other PCF8534As in the cascade contribute additional segment outputs but their backplane outputs are left open-circuit (see Figure 22). Table 18. Addressing cascaded PCF8534A Cluster Bit SA0 Pin A2 Pin A1 Pin A0 Device 100000 0011 0102 0113 1004 1015 1106 1117 210008 0019 01010 01111 10012 10113 11014 11115 |
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