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OMAP3530-HiRel датащи(PDF) 22 Page - Texas Instruments

номер детали OMAP3530-HiRel
подробное описание детали  OMAP3525-HiRel and OMAP3530-HiRel Applications Processors
PDF  239 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI - Texas Instruments

OMAP3530-HiRel датащи(HTML) 22 Page - Texas Instruments

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OMAP3525-HiRel and OMAP3530-HiRel Applications Processors
SPRS599 – JUNE 2009
www.ti.com
Table 2-1. Ball Characteristics (CBB Pkg.) (continued)
BALL
BALL
PIN
MODE [4]
TYPE [5]
BALL
BALL
RESET
POWER [9]
HYS
BUFFER
PULL
IO
BOTTOM [1]
TOP [2]
NAME [3]
RESET
RESET
REL.
[10]
STRENGTH
U/D
CELL [13]
STATE [6]
REL.
MODE [8]
(mA) [11]
TYPE
STATE [7]
[12]
AF5
NA
mcbsp3_ clkx
0
IO
L
L
7
VDDS
Yes
4
PU/ PD
LVCMOS
uart2_tx
1
O
gpio_142
4
IO
hsusb3_tll_ data6
5
IO
safe_mode
7
AE5
NA
mcbsp3_fsx
0
IO
L
L
7
VDDS
Yes
4
PU/ PD
LVCMOS
uart2_rx
1
I
gpio_143
4
IO
hsusb3_tll_ data7
5
IO
safe_mode
7
AB26
NA
uart2_cts
0
I
H
H
7
VDDS
Yes
4
PU/ PD
LVCMOS
mcbsp3_dx
1
IO
gpt9_pwm_evt
2
IO
gpio_144
4
IO
safe_mode
7
AB25
NA
uart2_rts
0
O
H
H
7
VDDS
Yes
4
PU/ PD
LVCMOS
mcbsp3_dr
1
I
gpt10_pwm_evt
2
IO
gpio_145
4
IO
safe_mode
7
AA25
NA
uart2_tx
0
O
H
H
7
VDDS
Yes
4
PU/ PD
LVCMOS
mcbsp3_ clkx
1
IO
gpt11_pwm _evt
2
IO
gpio_146
4
IO
safe_mode
7
AD25
NA
uart2_rx
0
I
H
H
7
VDDS
Yes
4
PU/ PD
LVCMOS
mcbsp3_fsx
1
IO
gpt8_pwm_evt
2
IO
gpio_147
4
IO
safe_mode
7
AA8
NA
uart1_tx
0
O
L
L
7
VDDS
Yes
4
PU/ PD
LVCMOS
gpio_148
4
IO
safe_mode
7
AA9
NA
uart1_rts
0
O
L
L
7
VDDS
Yes
4
PU/ PD
LVCMOS
gpio_149
4
IO
safe_mode
7
W8
NA
uart1_cts
0
I
L
L
7
VDDS
Yes
4
PU/ PD
LVCMOS
gpio_150
4
IO
hsusb3_tll_clk
5
O
safe_mode
7
Y8
NA
uart1_rx
0
I
L
L
7
VDDS
Yes
4
PU/ PD
LVCMOS
mcbsp1_ clkr
2
IO
mcspi4_clk
3
IO
gpio_151
4
IO
safe_mode
7
AE1
NA
mcbsp4_ clkx
0
IO
L
L
7
VDDS
Yes
4
PU/ PD
LVCMOS
gpio_152
4
IO
hsusb3_tll_ data1
5
IO
mm3_txse0
6
IO
safe_mode
7
AD1
NA
mcbsp4_dr
0
I
L
L
7
VDDS
Yes
4
PU/ PD
LVCMOS
gpio_153
4
IO
hsusb3_tll_ data0
5
IO
mm3_rxrcv
6
IO
TERMINAL DESCRIPTION
22
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