OMAP3530-HiRel datasheet(97/239 Pages) TI

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3.3 Recommended Operating Conditions

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

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SPRS599 – JUNE 2009

All OMAP3525 and OMAP3530 modules are used under the operating conditions contained in Table 3-3.

Note:

To avoid significant device degradation for commercial temperature OMAP3530/OMAP3525 devices

(–40

°C ≤ T

J ≤ 90°C), the device power-on hours (POH) must be limited to one of the following:

• 100K total POH when operating across all OPPs and keeping the time spent at OPP5 to less than 23K

POH.

• 50K total POH when operating exclusively at OPP5.

• 44K total POH with no restrictions to the proportion of these POH at operating points OPP1 - OPP5.

Note: Logic functions and parameter values are not assured out of the range specified in the

recommended operating conditions.

Table 3-3. Recommended Operating Conditions

PARAMETER

DESCRIPTION

MIN

NOM

MAX

UNIT

VDD1

OMAP processor logic supply

OPP5: Overdrive

VDD1NOM -

1.35

VDD1NOM +

(vdd_mpu_iva),

(0.05*VDD1NOM)

SmartReflex

OPP4: Mid-Overdrive

VDD1NOM -

1.27

VDD1NOM +

Disabled

(0.05*VDD1NOM)

OPP3: Nominal

VDD1NOM -

1.20

VDD1NOM +

(0.05*VDD1NOM)

OPP2: Low-Power

VDD1NOM -

1.05

VDD1NOM +

(0.05*VDD1NOM)

OPP1: Ultra Low-Power

VDD1NOM -

0.975

VDD1NOM +

(0.05*VDD1NOM)

VDD2 (vdd_core) OMAP core logic supply

(1)

OPP3: Nominal

VDD2NOM -

1.15

VDD2NOM +

SmartReflex

(0.05*VDD2NOM)

Disabled

OPP2: Low-Power

VDD2NOM -

1.05

VDD2NOM +

(0.05*VDD2NOM)

OPP1: Ultra Low-Power

VDD2NOM -

0.975

VDD2NOM +

(0.05*VDD2NOM)

vdds

Supply voltage for I/O macros

1.71

1.8

1.91

Noise (peak-peak)

mVpp

vdds_mem

Supply voltage for memory I/O macros

1.71

1.8

1.89

Noise (peak-peak)

mVpp

vdds_mmc1

Supply voltage range for MMC1

1.8-V mode

1.71

1.8

1.89

CMD, CLK and DAT[3:0] and for

3.0-V mode

2.7

3.0

3.3

memory stick I/Os

Noise (peak-peak)

1.8-V mode

mVpp

3.0-V mode

150

vdds_mmc1a

Second supply voltage range for

1.8-V mode

1.71

1.8

1.89

SIM I/Os and MMC1 DAT[7:4]

3.0-V mode

2.7

3.0

3.3

Noise (peak-peak)

1.8-V mode

mVpp

3.0-V mode

150

vdds_wkup_bg

Wakeup LDO

1.71

1.8

1.89

Noise (peak-peak)

mVpp

vdda_dac

Analog supply voltage for video DAC

1.71

1.8

1.89

Noise (peak-peak)

For a frequency of 0 to

mVpp

100 kHz

(For a frequency < 100

kHz, decreases 20dB /

sec)

(1)

Core logic includes interconnect, graphics processor, and peripherals.

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