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OMAP3530-HiRel датащи(PDF) 16 Page - Texas Instruments

номер детали OMAP3530-HiRel
подробное описание детали  OMAP3525-HiRel and OMAP3530-HiRel Applications Processors
PDF  239 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI - Texas Instruments

OMAP3530-HiRel датащи(HTML) 16 Page - Texas Instruments

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OMAP3525-HiRel and OMAP3530-HiRel Applications Processors
SPRS599 – JUNE 2009
www.ti.com
Table 2-1. Ball Characteristics (CBB Pkg.) (continued)
BALL
BALL
PIN
MODE [4]
TYPE [5]
BALL
BALL
RESET
POWER [9]
HYS
BUFFER
PULL
IO
BOTTOM [1]
TOP [2]
NAME [3]
RESET
RESET
REL.
[10]
STRENGTH
U/D
CELL [13]
STATE [6]
REL.
MODE [8]
(mA) [11]
TYPE
STATE [7]
[12]
gpio_56
4
IO
safe_mode
7
P8
NA
gpmc_ncs6
0
O
H
H
7
VDDS_ MEM
Yes
4
PU/ PD
LVCMOS
sys_ ndmareq3
1
I
mcbsp4_dx
2
IO
gpt11_pwm_evt
3
IO
gpio_57
4
IO
safe_mode
7
N8
NA
gpmc_ncs7
0
O
H
H
7
VDDS_ MEM
Yes
4
PU/ PD
LVCMOS
gpmc_io_dir
1
O
mcbsp4_fsx
2
IO
gpt8_pwm_evt
3
IO
gpio_58
4
IO
safe_mode
7
T4
W2
gpmc_clk
0
O
L
0
0
VDDS_ MEM
Yes
4
PU/ PD
LVCMOS
gpio_59
4
IO
safe_mode
7
F3
W1
gpmc_nadv_ale
0
O
0
0
0
VDDS_ MEM
No
4
NA
LVCMOS
G2
V2
gpmc_noe
0
O
1
1
0
VDDS_ MEM
No
4
NA
LVCMOS
F4
V1
gpmc_nwe
0
O
1
1
0
VDDS_ MEM
No
4
NA
LVCMOS
G3
AC12
gpmc_nbe0_cle
0
O
L
0
0
VDDS_ MEM
Yes
4
PU/ PD
LVCMOS
gpio_60
4
IO
safe_mode
7
U3
NA
gpmc_nbe1
0
O
L
L
7
VDDS_ MEM
Yes
4
PU/ PD
LVCMOS
gpio_61
4
IO
safe_mode
7
H1
AB10
gpmc_nwp
0
O
L
0
0
VDDS_ MEM
Yes
4
PU/ PD
LVCMOS
gpio_62
4
IO
safe_mode
7
M8
AB12
gpmc_wait0
0
I
H
H
0
VDDS_ MEM
Yes
NA
PU/ PD
LVCMOS
L8
AC10
gpmc_wait1
0
I
H
H
7
VDDS_ MEM
Yes
4
PU/ PD
LVCMOS
gpio_63
4
IO
safe_mode
7
K8
NA
gpmc_wait2
0
I
H
H
7
VDDS_ MEM
Yes
4
PU/ PD
LVCMOS
gpio_64
4
IO
safe_mode
7
J8
NA
gpmc_wait3
0
I
H
H
7
VDDS_ MEM
Yes
4
PU/ PD
LVCMOS
sys_ ndmareq1
1
I
gpio_65
4
IO
safe_mode
7
D28
NA
dss_pclk
0
O
H
H
7
VDDS
Yes
8
PU/ PD
LVCMOS
gpio_66
4
IO
safe_mode
7
D26
NA
dss_hsync
0
O
H
H
7
VDDS
Yes
8
PU/ PD
LVCMOS
gpio_67
4
IO
safe_mode
7
D27
NA
dss_vsync
0
O
H
H
7
VDDS
Yes
8
PU/ PD
LVCMOS
gpio_68
4
IO
safe_mode
7
E27
NA
dss_acbias
0
O
L
L
7
VDDS
Yes
8
PU/ PD
LVCMOS
gpio_69
4
IO
safe_mode
7
AG22
NA
dss_data0
0
IO
L
L
7
VDDS
Yes
8
PU/ PD
LVDS/ CMOS
uart1_cts
2
I
TERMINAL DESCRIPTION
16
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